Holger Vogt, Marcel Hendrix, Paolo Nenzi
January 1st, 2019
Locations
The project and download pages of ngspice may be found at
Ngspice home page http://ngspice.sourceforge.net/
Project page at sourceforge http://sourceforge.net/projects/ngspice/
Download page at sourceforge http://sourceforge.net/projects/ngspice/files/
Git source download http://sourceforge.net/scm/?type=cvs&group_id=38962
Status
This manual is a work in progress. Some todos are listed in Chapt. 24.3. More is surely needed. You are invited to report bugs, missing items, wrongly described items, bad English style etc.
How to use this manual
The manual is a `work in progress'. It may accompany a specific ngspice release, e.g. ngspice24 as manual version 24. If its name contains `Version xxplus', it describes the actual code status, found at the date of issue in the Git Source Code Management (SCM) tool. The manual is intended to provide a complete description of the ngspice functionality, its features, commands, or procedures. It is not a book about learning SPICE usage, but the novice user may find some hints how to start using ngspice. Chapter 21.1 gives a short introduction how to set up and simulate a small circuit. Chapter 32 is about compiling and installing ngspice from a tarball or the actual Git source code, which you may find on the ngspice web pages. If you are running a specific Linux distribution, you may check if it provides ngspice as part of the package. Some are listed here.
License
This document is covered by the Creative Commons Attribution ShareAlike (CCBYSA) v4.0..
Part of chapters 12 and 2527 are in the public domain.
Chapter 30 is covered by New BSD (chapt. 33.3.2).
Part I Ngspice User Manual
Table of Contents
Preface to the actual edition (as May 2018)
1.3 Analysis at Different Temperatures
2.1 General Structure and Conventions
2.8 .PARAM Parametric netlists
2.12 .IF ConditionControlled Netlist
2.13 Parameters, functions, expressions, and command scripts
Chapter 3 Circuit Elements and Models
3.1 General options and information
Chapter 4 Voltage and Current Sources
4.1 Independent Sources for Voltage or Current
Chapter 5 Nonlinear Dependent Sources (Behavioral Sources)
5.1 Bxxxx: Nonlinear dependent source (ASRC)
5.2 Exxxx: nonlinear voltage source
5.3 Gxxxx: nonlinear current source
5.4 Debugging a behavioral source
6.1 Lossless Transmission Lines
6.3 Uniform Distributed RC Lines
6.4 KSPICE Lossy Transmission Lines
8.1 Bipolar Junction Transistors (BJTs)
9.1 Junction FieldEffect Transistors (JFETs)
11.2 MOSFET models (NMOS/PMOS)
11.3 Power MOSFET model (VDMOS)
Chapter 12 MixedMode and Behavioral Modeling with XSPICE
12.1 Code Model Element & .MODEL Cards
12.5 Predefined Node Types for event driven simulation
Chapter 13 Verilog A Device models
13.3 How to integrate a VerilogA model into ngspice
Chapter 14 MixedLevel Simulation (ngspice with TCAD)
Chapter 15 Analyses and Output Control (batch mode)
15.1 Simulator Variables (.options)
15.4 Measurements after AC, DC and Transient Analysis
15.5 Safe Operating Area (SOA) warning messages
15.7 Measuring current through device terminals
16.3 Command line options for starting ngspice and ngnutmeg
16.5 Standard configuration file spinit
16.6 User defined configuration file .spiceinit
16.10 Ngspice on multicore processors using OpenMP
16.12 Ngspice control via input, output fifos
16.15 Reporting bugs and errors
Chapter 17 Interactive Interpreter
17.2 Expressions, Functions, and Constants
17.7 Internally predefined variables
17.9 Scattering parameters (sparameters)
Chapter 18 Ngspice User Interfaces
18.1 MS Windows Graphical User Interface
18.6 Postscript printing options
18.8 Integration with CAD software and `third party' GUIs
Chapter 19 ngspice as shared library or dynamic link library
19.2 Linking shared ngspice to a calling application
19.4 General remarks on using the API
20.7 MS Windows 32 Bit binaries
21.1 AC coupled transistor amplifier
21.5 FourBit Binary Adder (Bipolar)
21.6 FourBit Binary Adder (MOS)
21.7 TransmissionLine Inverter
Chapter 22 Statistical circuit analysis
22.2 Using random param(eters)
22.3 Behavioral sources (B, E, G, R, L, C) with random control
22.4 ngspice scripting language
22.6 Data evaluation with Gnuplot
Chapter 23 Circuit optimization with ngspice
23.1 Optimization of a circuit
23.2 ngspice optimizer using ngspice scripts
23.3 ngspice optimizer using tclspice
23.4 ngspice optimizer using a Python script
23.5 ngspice optimizer using ASCO
24.2 Acronyms and Abbreviations
Part II XSPICE Software User's Manual
25.1 ngspice with the XSPICE option
25.2 The XSPICE Code Model Subsystem
Chapter 26 Execution Procedures
26.1 Simulation and Modeling Overview
26.2 Circuit Description Syntax
26.3 How to create code models
27.1 Amplifier with XSPICE model `gain'
Chapter 28 Code Models and UserDefined Nodes
28.1 Code Model Data Type Definitions
28.3 Creating UserDefined Nodes
28.4 Adding a new code model library
28.5 Compiling and loading the new code model (library)
28.6 Interface Specification File
28.8 UserDefined Node Definition File
29.1 Preprocessor Error Messages
29.3 Code Model Error Messages
Chapter 30 CIDER User’s Manual
Chapter 31 Model and Device Parameters
31.1 Accessing internal device parameters
31.3 Voltage and current sources
32.1 Ngspice Installation under Linux (and other 'UNIXes')
32.2 Ngspice Compilation under Windows OS
Chapter 33 Copyrights and licenses
33.4 Some notes on the historical evolvement of the ngspice licenses
Prefaces
Preface to the first edition
This manual has been assembled from different sources:
 The spice3f5 manual,
 the XSPICE user's manual,
 the CIDER user's manual
and some original material needed to describe the new features and the newly implemented models. This cut and paste approach, while not being orthodox, allowed ngspice to have a full manual in a fraction of the time that writing a completely new text would have required. The use of and LyX instead of info, which was the original encoding for the manual, further helped to reduce the writing effort and improved the quality of the result, at the expense of an online version of the manual but, due to the complexity of the software I hardly think that users will ever want to read an online text version.
In writing this text I followed the spice3f5 manual, both in the chapter sequence and presentation of material, mostly because that was already the user manual of SPICE.
Ngspice is an open source software, users can download the source code, compile, and run it. This manual has an entire chapter describing program compilation and available options to help users in building ngspice (see Chapt. 32). The source package already comes with all `safe' options enabled by default, and activating the others can produce unpredictable results and thus is recommended to expert users only. This is the first ngspice manual and I have removed all the historical material that described the differences between ngspice and spice3, since it was of no use for the user and not so useful for the developer who can look for it in the Changelogs of in the revision control system.
I want to acknowledge the work done by Emmanuel Rouat and Arno W. Peters for converting the original spice3f documentation to TeXinfo. Their effort gave ngspice users the only available documentation that described the changes for many years. A good source of ideas for this manual came from the online spice3f manual written by Charles D.H. Williams (Spice3f5 User Guide), constantly updated and useful for its many insights.
As always, errors, omissions and unreadable phrases are only my fault.
Paolo Nenzi
Roma, March 24th 2001
Indeed. At the end of the day, this is engineering, and one learns to live
within the limitations of the tools.
Kevin Aylward, Warden of the King's Ale
Preface to the actual edition (as May 2018)
Due to the wealth of new material and options in ngspice the actual order of chapters has been revised. Several new chapters have been added. The LyX text processor has allowed adding internal cross references. The PDF format has become the standard format for distribution of the manual. Within each new ngspice distribution (starting with ngspice21) a manual edition is provided reflecting the ngspice status at the time of distribution. At the same time, located at ngspice manuals, the manual is constantly updated. Every new ngspice feature should enter this manual as soon as it has been made available in the Git source code master branch.
Holger Vogt
Mülheim, 2018
Acknowledgments
ngspice contributors
Spice3 and CIDER were originally written at The University of California at Berkeley (USA).
XSPICE has been provided by Georgia Institute of Technology, Atlanta (USA).
Since then, there have been many people working on the software, most of them releasing patches to the original code through the Internet.
The following people have contributed in some way:
Vera Albrecht,
Cecil Aswell,
Giles C. Billingsley,
Phil Barker,
Steven Borley,
Stuart Brorson,
Mansun Chan,
Wayne A. Christopher,
Al Davis,
Glao S. Dezai,
Jon Engelbert,
Daniele Foci,
Noah Friedman,
David A. Gates,
Alan Gillespie,
John Heidemann,
Marcel Hendrix,
Jeffrey M. Hsu,
JianHui Huang,
S. Hwang,
Chris Inbody,
Gordon M. Jacobs,
MinChie Jeng,
Beorn Johnson,
Stefan Jones,
Kenneth H. Keller,
Francesco Lannutti,
Robert Larice,
Mathew Lew,
Robert Lindsell,
Weidong Liu,
Kartikeya Mayaram,
Richard D. McRoberts,
Manfred Metzger,
Wolfgang Muees,
Paolo Nenzi,
Gary W. Ng,
Hong June Park,
Stefano Perticaroli,
Arno Peters,
SerbanMihai Popescu,
Georg Post,
Thomas L. Quarles,
Emmanuel Rouat,
JeanMarc Routure,
Jaijeet S. Roychowdhury,
Lionel Sainte Cluque,
Takayasu Sakurai,
Amakawa Shuhei,
Kanwar Jit Singh,
Bill Swartz,
Hitoshi Tanaka,
Steve Tell,
Andrew Tuckey,
Andreas Unger,
Holger Vogt,
Dietmar Warning,
Michael Widlok,
Charles D.H. Williams,
Antony Wilson,
and many others...
If someone helped in the development and has not been inserted in this list then this omission was unintentional. If you feel you should be on this list then please write to <ngspicedevel@lists.sourceforge.net>. Do not be shy, we would like to make a list as complete as possible.
Introduction
Ngspice is a generalpurpose circuit simulation program for nonlinear and linear analyses. Circuits may contain resistors, capacitors, inductors, mutual inductors, independent or dependent voltage and current sources, lossless and lossy transmission lines, switches, uniform distributed RC lines, and the five most common semiconductor devices: diodes, BJTs, JFETs, MESFETs, and MOSFETs.
Some introductory remarks on how to use ngspice may be found in Chapt. 21.
Ngspice is an update of Spice3f5, the last Berkeley's release of Spice3 simulator family. Ngspice is being developed to include new features to existing Spice3f5 and to fix its bugs. Improving a complex software like a circuit simulator is a very hard task and, while some improvements have been made, most of the work has been done on bug fixing and code refactoring.
Ngspice has builtin models for the semiconductor devices, and the user need specify only the pertinent model parameter values. There are three models for bipolar junction transistors, all based on the integralcharge model of Gummel and Poon; however, if the GummelPoon parameters are not specified, the basic model (BJT) reduces to the simpler EbersMoll model. In either case and in either models, charge storage effects, ohmic resistances, and a currentdependent output conductance may be included. The second bipolar model BJT2 adds dc current computation in the substrate diode. The third model (VBIC) contains further enhancements for advanced bipolar devices.
The semiconductor diode model can be used for either junction diodes or Schottky barrier diodes. There are two models for JFET: the first (JFET) is based on the model of Shichman and Hodges, the second (JFET2) is based on the ParkerSkellern model. All the original six MOSFET models are implemented: MOS1 is described by a squarelaw IV characteristic, MOS2 [1] is an analytical model, while MOS3 [1] is a semiempirical model; MOS6 [2] is a simple analytic model accurate in the short channel region; MOS9, is a slightly modified Level 3 MOSFET model  not to confuse with Philips level 9; BSIM 1 [3, 4]; BSIM2 [5] are the old BSIM (Berkeley Shortchannel IGFET Model) models. MOS2, MOS3, and BSIM include secondorder effects such as channellength modulation, subthreshold conduction, scatteringlimited velocity saturation, smallsize effects, and charge controlled capacitances. The recent MOS models for submicron devices are the BSIM3 (Berkeley BSIM3 web page) and BSIM4 (Berkeley BSIM4 web page) models. Silicononinsulator MOS transistors are described by the SOI models from the BSIMSOI family (Berkeley BSIMSOI web page) and the STAG [18] one. There is partial support for a couple of HFET models and one model for MESA devices.
Ngspice supports mixedlevel simulation and provides a direct link between technology parameters and circuit performance. A mixedlevel circuit and device simulator can provide greater simulation accuracy than a standalone circuit or device simulator by numerically modeling the critical devices in a circuit. Compact models can be used for all other devices. The mixedlevel extensions to ngspice is CIDER, a mixedlevel circuit and device simulator integrated into ngspice code.
Ngspice supports mixedsignal simulation through the integration of XSPICE code. XSPICE software, developed as an extension to Spice3C1 by GeorgiaTech, has been enhanced and ported to ngspice to provide `board' level and mixedsignal simulation.
The XSPICE extension enables pure digital simulation as well.
New devices can be added to ngspice by several means: behavioral B, E or Gsources, the XSPICE codemodel interface for Clike device coding, and the ADMS interface based on VerilogA and XML.
Finally, numerous small bugs have been discovered and fixed, and the program has been ported to a wider variety of computing platforms.
Simulation Algorithms
Computerbased circuit simulation is often used as a tool by designers, test engineers, and others who want to analyze the operation of a design without examining the physical circuit. Simulation allows you to change quickly the parameters of many of the circuit elements to determine how they affect the circuit response. Often it is difficult or impossible to change these parameters in a physical circuit.
However, to be practical, a simulator must execute in a reasonable amount of time. The key to efficient execution is choosing the proper level of modeling abstraction for a given problem. To support a given modeling abstraction, the simulator must provide appropriate algorithms.
Historically, circuit simulators have supported either an analog simulation algorithm or a digital simulation algorithm. Ngspice inherits the XSPICE framework and supports both analog and digital algorithms and is a `mixedmode' simulator.
Analog Simulation
Analog simulation focuses on the linear and nonlinear behavior of a circuit over a continuous time or frequency interval. The circuit response is obtained by iteratively solving Kirchhoff's Laws for the circuit at time steps selected to ensure the solution has converged to a stable value and that numerical approximations of integrations are sufficiently accurate. Since Kirchhoff's laws form a set of simultaneous equations, the simulator operates by solving a matrix of equations at each time point. This matrix processing generally results in slower simulation times when compared to digital circuit simulators.
The response of a circuit is a function of the applied sources. Ngspice offers a variety of source types including DC, sinewave, and pulse. In addition to specifying sources, the user must define the type of simulation to be run. This is termed the `mode of analysis'. Analysis modes include DC analysis, AC analysis, and transient analysis. For DC analysis, the timevarying behavior of reactive elements is neglected and the simulator calculates the DC solution of the circuit. Swept DC analysis may also be accomplished with ngspice. This is simply the repeated application of DC analysis over a range of DC levels for the input sources. For AC analysis, the simulator determines the response of the circuit, including reactive elements to smallsignal sinusoidal inputs over a range of frequencies. The simulator output in this case includes amplitudes and phases as a function of frequency. For transient analysis, the circuit response, including reactive elements, is analyzed to calculate the behavior of the circuit as a function of time.
Digital Simulation
Digital circuit simulation differs from analog circuit simulation in several respects. A primary difference is that a solution of Kirchhoff's laws is not required. Instead, the simulator must only determine whether a change in the logic state of a node has occurred and propagate this change to connected elements. Such a change is called an `event'.
When an event occurs, the simulator examines only those circuit elements that are affected by the event. As a result, matrix analysis is not required in digital simulators. By comparison, analog simulators must iteratively solve for the behavior of the entire circuit because of the forward and reverse transmission properties of analog components. This difference results in a considerable computational advantage for digital circuit simulators, which is reflected in the significantly greater speed of digital simulations.
MixedSignal Simulation
Modern circuits often contain a mix of analog and digital circuits. To simulate such circuits efficiently and accurately a mix of analog and digital simulation techniques is required. When analog simulation algorithms are combined with digital simulation algorithms, the result is termed `mixedmode simulation'.
Two basic methods of implementing mixedmode simulation used in practice are the `native mode' and `glued mode' approaches. Native mode simulators implement both an analog algorithm and a digital algorithm in the same executable. Glued mode simulators actually use two simulators, one of which is analog and the other digital. This type of simulator must define an input/output protocol so that the two executables can communicate with each other effectively. The communication constraints tend to reduce the speed, and sometimes the accuracy, of the complete simulator. On the other hand, the use of a glued mode simulator allows the component models developed for the separate executables to be used without modification.
Ngspice is a native mode simulator providing both analog and eventbased simulation in the same executable. The underlying algorithms of ngspice (coming from XSPICE and its Code Model Subsystem) allow use of all the standard SPICE models, provide a predefined collection of the most common analog and digital functions, and provide an extensible base on which to build additional models.
UserDefined Nodes
Ngspice supports creation of `UserDefined Node' types. UserDefined Node types allow you to specify nodes that propagate data other than voltages, currents, and digital states. Like digital nodes, UserDefined Nodes use eventdriven simulation, but the state value may be an arbitrary data type. A simple example application of UserDefined Nodes is the simulation of a digital signal processing filter algorithm. In this application, each node could assume a real or integer value. More complex applications may define types that involve complex data such as digital data vectors or even nonelectronic data.
Ngspice digital simulation is actually implemented as a special case of this UserDefined Node capability where the digital state is defined by a data structure that holds a Boolean logic state and a strength value.
MixedLevel Simulation
Ngspice can simulate numerical device models for diodes and transistors in two different ways, either through the integrated DSIM simulator or interfacing to GSS TCAD system. DSIM is an internal Cbased device simulator that is part of the CIDER simulator, the mixedlevel simulator based on SPICE3f5. CIDER within ngspice provides circuit analyses, compact models for semiconductor devices, and one or twodimensional numerical device models.
CIDER (DSIM)
CIDER integrates the DSIM simulator with Spice3. It provides accurate, one and twodimensional numerical device models based on the solution of Poisson's equation, and the electron and hole currentcontinuity equations. DSIM incorporates many of the same basic physical models found in the Stanford twodimensional device simulator PISCES. Input to CIDER consists of a SPICElike description of the circuit and its compact models, and PISCESlike descriptions of the structures of numerically modeled devices. As a result, CIDER should seem familiar to designers already accustomed to these two tools. The CIDER input format has great flexibility and allows access to physical model parameters. New physical models have been added to allow simulation of stateoftheart devices. These include transverse field mobility degradation important in scaleddown MOSFETs and a polysilicon model for polyemitter bipolar transistors. Temperature dependence has been included over the range from 50C to 150C. The numerical models can be used to simulate all the basic types of semiconductor devices: resistors, MOS capacitors, diodes, BJTs, JFETs and MOSFETs. BJTs and JFETs can be modeled with or without a substrate contact. Support has been added for the management of device internal states. Postprocessing of device states can be performed using the ngnutmeg user interface.
GSS TCAD
GSS is a TCAD software that enables twodimensional numerical simulation of semiconductor device with wellknown driftdiffusion and hydrodynamic method. GSS has Basic DDM (driftdiffusion method) solver, Lattice Temperature Corrected DDM solver, EBM (energy balance method) solver and Quantum corrected DDM solver based on densitygradient theory. The GSS program is directed via input statements by a user specified disk file. Supports triangle mesh generation and adaptive mesh refinement. Employs PMI (physical model interface) to support various materials, including compound semiconductor materials such as SiGe and AlGaAs. Supports DC sweep, transient and AC sweep calculations. The device can be stimulated by voltage or current source(s).
GSS is no longer updated, but is still available as open source as a limited edition of the commercial GENIUS TCAD tool. This interface has not been tested with actual ngspice versions and may need some maintainance efforts.
Supported Analyses
The ngspice simulator supports the following different types of analysis:
 DC Analysis (Operating Point and DC Sweep)
 AC SmallSignal Analysis
 Transient Analysis
 PoleZero Analysis
 SmallSignal Distortion Analysis
 Sensitivity Analysis
 Noise Analysis
Applications that are exclusively analog can make use of all analysis modes with the exception of Code Model subsystem that do not implements PoleZero, Distortion, Sensitivity and Noise analyses. Eventdriven applications that include digital and UserDefined Node types may make use of DC (operating point and DC sweep) and Transient only.
In order to understand the relationship between the different analyses and the two underlying simulation algorithms of ngspice, it is important to understand what is meant by each analysis type. This is detailed below.
DC Analysis
The dc analysis portion of ngspice determines the dc operating point of the circuit with inductors shorted and capacitors opened. The dc analysis options are specified on the .DC, .TF, and .OP control lines.
There is assumed to be no time dependence on any of the sources within the system description. The simulator algorithm subdivides the circuit into those portions that require the analog simulator algorithm and such that require the eventdriven algorithm. Each subsystem block is then iterated to solution, with the interfaces between analog nodes and eventdriven nodes iterated for consistency across the entire system.
Once stable values are obtained for all nodes in the system, the analysis halts and the results may be displayed or printed out as you request them.
A dc analysis is automatically performed prior to a transient analysis to determine the transient initial conditions, and prior to an ac smallsignal analysis to determine the linearized, smallsignal models for nonlinear devices. If requested, the dc smallsignal value of a transfer function (ratio of output variable to input source), input resistance, and output resistance is also computed as a part of the dc solution. The dc analysis can also be used to generate dc transfer curves: a specified independent voltage, current source, resistor or temperature is stepped over a userspecified range and the dc output variables are stored for each sequential source value.
AC SmallSignal Analysis
AC analysis is limited to analog nodes and represents the small signal, sinusoidal solution of the analog system described at a particular frequency or set of frequencies. This analysis is similar to the DC analysis in that it represents the steadystate behavior of the described system with a single input node at a given set of stimulus frequencies.
The program first computes the dc operating point of the circuit and determines linearized, smallsignal models for all of the nonlinear devices in the circuit. The resultant linear circuit is then analyzed over a userspecified range of frequencies. The desired output of an ac smallsignal analysis is usually a transfer function (voltage gain, transimpedance, etc). If the circuit has only one ac input, it is convenient to set that input to unity and zero phase, so that output variables have the same value as the transfer function of the output variable with respect to the input.
Transient Analysis
Transient analysis is an extension of DC analysis to the time domain. A transient analysis begins by obtaining a DC solution to provide a point of departure for simulating timevarying behavior. Once the DC solution is obtained, the timedependent aspects of the system are reintroduced, and the two simulator algorithms incrementally solve for the time varying behavior of the entire system. Inconsistencies in node values are resolved by the two simulation algorithms such that the timedependent waveforms created by the analysis are consistent across the entire simulated time interval. Resulting timevarying descriptions of node behavior for the specified time interval are accessible to you.
All sources that are not time dependent (for example, power supplies) are set to their dc value. The transient time interval is specified on a .TRAN control line.
PoleZero Analysis
The polezero analysis portion of Ngspice computes the poles and/or zeros in the smallsignal ac transfer function. The program first computes the dc operating point and then determines the linearized, smallsignal models for all the nonlinear devices in the circuit. This circuit is then used to find the poles and zeros of the transfer function. Two types of transfer functions are allowed: one of the form (output voltage)/(input voltage) and the other of the form (output voltage)/(input current). These two types of transfer functions cover all the cases and one can find the poles/zeros of functions like input/output impedance and voltage gain. The input and output ports are specified as two pairs of nodes. The polezero analysis works with resistors, capacitors, inductors, linearcontrolled sources, independent sources, BJTs, MOSFETs, JFETs and diodes. Transmission lines are not supported. The method used in the analysis is a suboptimal numerical search. For large circuits it may take a considerable time or fail to find all poles and zeros. For some circuits, the method becomes `lost' and finds an excessive number of poles or zeros.
SmallSignal Distortion Analysis
The distortion analysis portion of Ngspice computes steadystate harmonic and intermodulation products for small input signal magnitudes. If signals of a single frequency are specified as the input to the circuit, the complex values of the second and third harmonics are determined at every point in the circuit. If there are signals of two frequencies input to the circuit, the analysis finds out the complex values of the circuit variables at the sum and difference of the input frequencies, and at the difference of the smaller frequency from the second harmonic of the larger frequency. Distortion analysis is supported for the following nonlinear devices:
 Diodes (DIO),
 BJT,
 JFET (level 1),
 MOSFETs (levels 1, 2, 3, 9, and BSIM1),
 MESFET (level 1).
All linear devices are automatically supported by distortion analysis. If there are switches present in the circuit, the analysis continues to be accurate provided the switches do not change state under the small excitations used for distortion calculations.
If a device model does not support direct small signal distortion analysis, please use the Fourier of FFT statements and evaluate the output per scripting.
Sensitivity Analysis
Ngspice will calculate either the DC operatingpoint sensitivity or the AC smallsignal sensitivity of an output variable with respect to all circuit variables, including model parameters. Ngspice calculates the difference in an output variable (either a node voltage or a branch current) by perturbing each parameter of each device independently. Since the method is a numerical approximation, the results may demonstrate second order effects in highly sensitive parameters, or may fail to show very low but nonzero sensitivity. Further, since each variable is perturb by a small fraction of its value, zerovalued parameters are not analyzed (this has the benefit of reducing what is usually a very large amount of data).
Noise Analysis
The noise analysis portion of Ngspice gives the devicegenerated noise for a given circuit. When provided with an input source and an output port, the analysis calculates the noise contributions of each device, and each noise generator within the device, to the output port voltage. It also calculates the equivalent input noise of the circuit, based on the output noise. This is done for every frequency point in a specified range  the calculated value of the noise corresponds to the spectral density of the circuit variable viewed as a stationary Gaussian stochastic process. After calculating the spectral densities, noise analysis integrates these values over the specified frequency range to arrive at the total noise voltage and current over this frequency range. The calculated values correspond to the variance of the circuit variables viewed as stationary Gaussian processes.
Periodic Steady State Analysis
Experimental code.
PSS is a radio frequency periodical largesignal dedicated analysis. The implementation is based on a time domain shooting method that make use of transient analysis. As it is in early development stage, PSS performs analysis only on autonomous circuits, meaning that it is able to predict fundamental frequency and (harmonic) amplitude(s) for oscillators, VCOs, etc.. The algorithm is based on a search of the minimum error vector defined as the difference of RHS vectors between two occurrences of an estimated period. Convergence is reached when the mean of this error vector decreases below a given threshold parameter. Results of PSS are the basis of periodical largesignal analyses like PAC or PNoise.
Analysis at Different Temperatures
Temperature, in ngspice, is a property associated to the entire circuit, rather than an analysis option. Circuit temperature has a default (nominal) value of 27°C (300.15 K) that can be changed using the TEMP option in an .option control line (see 15.1.1) or by the .TEMP line (see 2.11), which has precedence over the .option TEMP line. All analyses are, thus, performed at circuit temperature, and if you want to simulate circuit behavior at different temperatures you should prepare a netlist for each temperature.
All input data for ngspice is assumed to have been measured at the circuit nominal temperature. This value can further be overridden for any device that models temperature effects by specifying the TNOM parameter on the .model itself. Individual instances may further override the circuit temperature through the specification of TEMP and DTEMP parameters on the instance. The two options are not independent even if you can specify both on the instance line, the TEMP option overrides DTEMP. The algorithm to compute instance temperature is described below:
IF TEMP is specified THEN
instance_temperature = TEMP
ELSE IF
instance_temperature = circuit_temperature + DTEMP
END IF
Algorithm 1.1: Instance temperature computation
Temperature dependent support is provided for all devices except voltage and current sources (either independent and controlled) and BSIM models. BSIM MOSFETs have an alternate temperature dependency scheme that adjusts all of the model parameters before input to ngspice.
For details of the BSIM temperature adjustment, see [6] and [7]. Temperature appears explicitly in the exponential terms of the BJT and diode model equations. In addition, saturation currents have a builtin temperature dependence. The temperature dependence of the saturation current in the BJT models is determined by:
[\begin{array}{ll} {I_{S}\left( T_{1} \right) = I_{S}\left( T_{0} \right)\left( \frac{T_{1}}{T_{0}} \right)^{XTI}\exp\left( \frac{E_{g}q\left( {T_{1}T_{0}} \right)}{k\left( {T_{1}  T_{0}} \right)} \right)} & \ \end{array}]
where (k) is Boltzmann's constant, (q) is the electronic charge, (E_{g}) is the energy gap model parameter, and (XTI) is the saturation current temperature exponent (also a model parameter, and usually equal to 3).
The temperature dependence of forward and reverse beta is according to the formula:
[\begin{array}{ll} {B\left( T_{1} \right) = B\left( T_{0} \right)\left( \frac{T_{1}}{T_{0}} \right)^{XTB}} & \ \end{array}]
where (T_{0}) and (T_{1}) are in degrees Kelvin, and (XTB) is a usersupplied model parameter. Temperature effects on beta are carried out by appropriate adjustment to the values of (B_{F}), (I_{SE}), (B_{R}), and (I_{SC}) (SPICE model parameters BF, ISE, BR, and ISC, respectively).
Temperature dependence of the saturation current in the junction diode model is determined by:
[\begin{array}{ll} {I_{S}\left( T_{1} \right) = I_{S}\left( T_{0} \right)\left( \frac{T_{1}}{T_{0}} \right)^{\frac{XTI}{N}}\exp\left( \frac{E_{g}q\left( {T_{1}T_{0}} \right)}{Nk\left( {T_{1}  T_{0}} \right)} \right)} & \ \end{array}]
where (N) is the emission coefficient model parameter, and the other symbols have the same meaning as above. Note that for Schottky barrier diodes, the value of the saturation current temperature exponent, (XTI), is usually 2. Temperature appears explicitly in the value of junction potential, U (in Ngspice PHI), for all the device models.
The temperature dependence is determined by:
[\begin{array}{ll} {U\left( T \right) = \frac{kT}{q}\ln\left( \frac{N_{a}N_{d}}{N_{i}\left( T \right)^{2}} \right)} & \ \end{array}]
where (k) is Boltzmann's constant, (q) is the electronic charge, (N_{a}) is the acceptor impurity density, (N_{d}) is the donor impurity density, (N_{i}) is the intrinsic carrier concentration, and (E_{g}) is the energy gap. Temperature appears explicitly in the value of surface mobility, (M_{0})(or (U_{0})), for the MOSFET model.
The temperature dependence is determined by:
[\begin{array}{ll} {M_{0}\left( T \right) = \frac{M_{0}\left( T_{0} \right)}{\left( \frac{T}{T_{0}} \right)^{1.5}}} & \ \end{array}]
The effects of temperature on resistors, capacitor and inductors is modeled by the formula:
[\begin{array}{ll} {R\left( T \right) = R\left( T_{0} \right)\left\lbrack {1 + TC_{1}\left( {T  T_{0}} \right) + TC_{2}\left( {T  T_{0}} \right)^{2}} \right\rbrack} & \ \end{array}]
where (T) is the circuit temperature, (T_{0}) is the nominal temperature, and (TC_{1}) and (TC_{2}) are the first and second order temperature coefficients.
Convergence
Ngspice uses the NewtonRaphson algorithm to solve nonlinear equations arising from circuit description. The NR algorithm is interactive and terminates when both of the following conditions hold:
 The nonlinear branch currents converge to within a tolerance of 0.1% or 1 picoamp (1.0e12 Amp), whichever is larger.
 The node voltages converge to within a tolerance of 0.1% or 1 microvolt (1.0e6 Volt), whichever is larger.
Voltage convergence criterion
The algorithm has reached convergence when the difference between the last iteration (k) and the current one ((\left. k + 1 \right))
[\begin{array}{ll} {\left {v_{n}^{({k + 1})}  v_{n}^{(k)}} \right \leq \mathtt{RELTOL} v_{n_{max}} + \mathtt{VNTOL},} & \ \end{array}]
where
[\begin{array}{ll} {v_{n_{max}} = \max\left( {\left v_{n}^{({k + 1})} \right,\left v_{n}^{(k)} \right} \right).} & \ \end{array}]
The RELTOL (RELative TOLerance) parameter, which default value is (10^{ 3}), specifies how small the solution update must be, relative to the node voltage, to consider the solution to have converged. The VNTOL (absolute convergence) parameter, which has (1\mu V) as default value, becomes important when node voltages have near zero values. The relative parameter alone, in such case, would need too strict tolerances, perhaps lower than computer roundoff error, and thus convergence would never be achieved. VNTOL forces the algorithm to consider as converged any node whose solution update is lower than its value.
Current convergence criterion
Ngspice checks the convergence on the nonlinear functions that describe the nonlinear branches in circuit elements. In semiconductor devices the functions defines currents through the device and thus the name of the criterion.
Ngspice computes the difference between the value of the nonlinear function computed for the last voltage and the linear approximation of the same current computed with the actual voltage
[\begin{array}{ll} {\left {\hat{i_{branch}^{({k + 1})}}  i_{branch}^{(k)}} \right \leq \mathtt{RELTOL} i_{br_{max}} + \mathtt{ABSTOL},} & \ \end{array}]
where
[\begin{array}{ll} {i_{br_{max}} = \max\left( {\hat{i_{branch}^{({k + 1})}},i_{branch}^{(k)}} \right).} & \ \end{array}]
In the two expressions above, the (\hat{i_{branch}}) indicates the linear approximation of the current.
Convergence failure
Although the algorithm used in ngspice has been found to be very reliable, in some cases it fails to converge to a solution. When this failure occurs, the program terminates the job. Failure to converge in dc analysis is usually due to an error in specifying circuit connections, element values, or model parameter values. Regenerative switching circuits or circuits with positive feedback probably will not converge in the dc analysis unless the OFF option is used for some of the devices in the feedback path, .nodeset control line is used to force the circuit to converge to the desired state.
Circuit Description
General Structure and Conventions
Input file structure
The circuit to be analyzed is described to ngspice by a set of element instance lines, which define the circuit topology and element instance values, and a set of control lines, which define the model parameters and the run controls. All lines are assembled in an input file to be read by ngspice. Two lines are essential:
 The first line in the input file must be the title, which is the only comment line that does not need any special character in the first place.
 The last line must be .end.
The order of the remaining lines is arbitrary (except, of course, that continuation lines must immediately follow the line being continued). This feature in the ngspice input language dates back to the punched card times where elements were written on separate cards (and cards frequently fell off). Leading white spaces in a line are ignored, as well as empty lines.
The lines described in sections 2.1 to 2.12 are typically used in the core of the input file, outside of a .control section (see 16.4.3). An exception is the .include includefile line (2.6) that may be placed anywhere in the input file. The contents of includefile will be inserted exactly in place of the .include line.
Circuit elements (device instances)
Each element in the circuit is a device instance specified by an instance line that contains:
 the element instance name,
 the circuit nodes to which the element is connected,
 and the values of the parameters that determine the electrical characteristics of the element.
The first letter of the element instance name specifies the element type. The format for the ngspice element types is given in the following manual chapters. In the rest of the manual, the strings XXXXXXX, YYYYYYY, and ZZZZZZZ denote arbitrary alphanumeric strings.
For example, a resistor instance name must begin with the letter R and can contain one or more characters. Hence, R, R1,** **RSE, ROUT, and R3AC2ZY are valid resistor names. Details of each type of device are supplied in a following section 3. Table 2.1 lists the element types available in ngspice, sorted by their first letter.
First letter

Element description

Comments, links

A

XSPICE code model


B

Behavioral (arbitrary) source


C

Capacitor


D

Diode


E

Voltagecontrolled voltage source (VCVS)


F

Currentcontrolled current source (CCCs)

linear (4.2.3)

G

Voltagecontrolled current source (VCCS)


H

Currentcontrolled voltage source (CCVS)

linear (4.2.4)

I

Current source


J

Junction field effect transistor (JFET)


K

Coupled (Mutual) Inductors


L

Inductor


M

Metal oxide field effect transistor (MOSFET)


N

Numerical device for GSS


O

Lossy transmission line


P

Coupled multiconductor line (CPL)


Q

Bipolar junction transistor (BJT)


R

Resistor


S

Switch (voltagecontrolled)


T

Lossless transmission line


U

Uniformly distributed RC line


V

Voltage source


W

Switch (currentcontrolled)


X

Subcircuit


Y

Single lossy transmission line (TXL)


Z

Metal semiconductor field effect transistor (MESFET)

Table 2.1: ngspice element types
Some naming conventions
Fields on a line are separated by one or more blanks, a comma, an equal (=) sign, or a left or right parenthesis; extra spaces are ignored. A line may be continued by entering a `+' (plus) in column 1 of the following line; ngspice continues reading beginning with column 2. A name field must begin with a letter (A through Z) and cannot contain any delimiters. A number field may be an integer field (12, 44), a floating point field (3.14159), either an integer or floating point number followed by an integer exponent (1e14, 2.65e3), or either an integer or a floating point number followed by one of the following scale factors:
Suffix

Name

Factor

T

Tera

10^{12}

G

Giga

10^{9}

Meg

Mega

10^{6}

K

Kilo

10^{3}

mil

Mil

25.4 × 10^{−6}

m

milli

10^{−3}

u

micro

10^{−6}

n

nano

10^{−9}

p

pico

10^{−12}

f

femto

10^{−15}

Table 2.2: Ngspice scale factors
Letters immediately following a number that are not scale factors are ignored, and letters immediately following a scale factor are ignored. Hence, 10, 10V, 10Volts, and 10Hz all represent the same number, and M, MA, MSec, and MMhos all represent the same scale factor. Note that 1000, 1000.0, 1000Hz, 1e3, 1.0e3, 1kHz, and 1k all represent the same number. Note that `M'* or *`m' denote `milli', i.e. (10^{ 3}). Suffix meg has to be used for (10^{6}).
Nodes names may be arbitrary character strings and are case insensitive, if ngspice is used in batch mode (16.4.1). If in interactive (16.4.2) or control (16.4.3) mode, node names may either be plain numbers or arbitrary character strings, not starting with a number. The ground node must be named `0' (zero). For compatibility reason gnd is accepted as ground node, and will internally be treated as a global node and be converted to `0'. If this is not feasible, you may switch the conversion off by setting set no_auto_gnd in one of the configuration files spinit or .spiceinit. Each circuit has to have a ground node (gnd or 0)! Note the difference in ngspice where the nodes are treated as character strings and not evaluated as numbers, thus `0' and 00 are distinct nodes in ngspice but not in SPICE2.
Ngspice requires that the following topological constraints are satisfied:
 The circuit cannot contain a loop of voltage sources and/or inductors and cannot contain a cutset of current sources and/or capacitors.
 Each node in the circuit must have a dc path to ground.
 Every node must have at least two connections except for transmission line nodes (to permit unterminated transmission lines) and MOSFET substrate nodes (which have two internal connections anyway).
Basic lines
.TITLE line
Examples:
POWER AMPLIFIER CIRCUIT
* additional lines following
*...
Test of CAM cell
* additional lines following
*...
The title line must be the first in the input file. Its contents are printed verbatim as the heading for each section of output.
As an alternative you may place a .TITLE <any title> line anywhere in your input deck. The first line of your input deck will be overridden by the contents of this line following the .TITLE statement.
.TITLE line example:
******************************
* additional lines following
*...
.TITLE Test of CAM cell
* additional lines following
*...
will internally be replaced by
Internal input deck:
Test of CAM cell
* additional lines following
*...
*TITLE Test of CAM cell
* additional lines following
*...
.END Line
Examples:
.end
The .end line must always be the last in the input file. Note that the period is an integral part of the name.
Comments
General Form:
* <any comment>
Examples:
* RF=1K Gain should be 100
* Check openloop gain and phase margin
The asterisk in the first column indicates that this line is a comment line. Comment lines may be placed anywhere in the circuit description.
Endofline comments
General Form:
<any command> $ <any comment>
Examples:
RF2=1K $ Gain should be 100
C1=10p $ Check openloop gain and phase margin
.param n1=1 //new value
ngspice supports comments that begin with double characters `$ ' (dollar plus space) or `//'. For readability you should precede each comment character with a space. ngspice will accept the single character `$'.
Please note that in .control sections the `;' character means `continuation' and can be used to put more than one statement on a line.
.MODEL Device Models
General form:
.model mname type(pname1=pval1 pname2=pval2 ... )
Examples:
.model MOD1 npn (bf=50 is=1e13 vbf=50)
Most simple circuit elements typically require only a few parameter values. However, some devices (semiconductor devices in particular) that are included in ngspice require many parameter values. Often, many devices in a circuit are defined by the same set of device model parameters. For these reasons, a set of device model parameters is defined on a separate .model line and assigned a unique model name. The device element lines in ngspice then refer to the model name.
For these more complex device types, each device element line contains the device name, the nodes the device is connected to, and the device model name. In addition, other optional parameters may be specified for some devices: geometric factors and an initial condition (see the following section on Transistors (8 to 11) and Diodes (7) for more details). mname in the above is the model name, and type is one of the following fifteen types:
Code

Model Type

R

Semiconductor resistor model

C

Semiconductor capacitor model

L

Inductor model

SW

Voltage controlled switch

CSW

Current controlled switch

URC

Uniform distributed RC model

LTRA

Lossy transmission line model

D

Diode model

NPN

NPN BJT model

PNP

PNP BJT model

NJF

Nchannel JFET model

PJF

Pchannel JFET model

NMOS

Nchannel MOSFET model

PMOS

Pchannel MOSFET model

NMF

Nchannel MESFET model

PMF

Pchannel MESFET model

VDMOS

Power MOS model

Table 2.3: Ngspice model types
Parameter values are defined by appending the parameter name followed by an equal sign and the parameter value. Model parameters that are not given a value are assigned the default values given below for each model type. Models are listed in the section on each device along with the description of device element lines. Model parameters and their default values are given in Chapt. 31.
.SUBCKT Subcircuits
A subcircuit that consists of ngspice elements can be defined and referenced in a fashion similar to device models. Subcircuits are the way ngspice implements hierarchical modeling, but this is not entirely true because each subcircuit instance is flattened during parsing, and thus ngspice is not a hierarchical simulator.
The subcircuit is defined in the input deck by a grouping of element cards delimited by the .subckt and the .ends cards (or the keywords defined by the substart and subend options (see 17.7)); the program then automatically inserts the defined group of elements wherever the subcircuit is referenced. Instances of subcircuits within a larger circuit are defined through the use of an instance card that begins with the letter `X'. A complete example of all three of these cards follows:
Example:
* The following is the instance card:
*
xdiv1 10 7 0 vdivide
* The following are the subcircuit definition cards:
*
.subckt vdivide 1 2 3
r1 1 2 10K
r2 2 3 5K
.ends
The above specifies a subcircuit with ports numbered `1', `2' and `3':
 Resistor `R1' is connected from port `1' to port `2', and has value 10 kOhms.
 Resistor `R2' is connected from port `2' to port `3', and has value 5 kOhms.
The instance card, when placed in an ngspice deck, will cause subcircuit port `1' to be equated to circuit node `10', while port `2' will be equated to node `7' and port `3' will equated to node `0'.
There is no limit on the size or complexity of subcircuits, and subcircuits may contain other subcircuits. An example of subcircuit usage is given in Chapt. 21.6.
.SUBCKT Line
General form:
.SUBCKT subnam N1 <N2 N3 ...>
Examples:
.SUBCKT OPAMP 1 2 3 4
A circuit definition is begun with a .SUBCKT line. subnam is the subcircuit name, and N1, N2, ... are the external nodes, which cannot be zero. The group of element lines that immediately follow the .SUBCKT line define the subcircuit. The last line in a subcircuit definition is the .ENDS line (see below). Control lines may not appear within a subcircuit definition; however, subcircuit definitions may contain anything else, including other subcircuit definitions, device models, and subcircuit calls (see below). Note that any device models or subcircuit definitions included as part of a subcircuit definition are strictly local (i.e., such models and definitions are not known outside the subcircuit definition). Also, any element nodes not included on the .SUBCKT line are strictly local, with the exception of 0 (ground) that is always global. If you use parameters, the .SUBCKT line will be extended (see 2.8.3).
.ENDS Line
General form:
.ENDS <SUBNAM>
Examples:
.ENDS OPAMP
The .ENDS line must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being terminated; if omitted, all subcircuits being defined are terminated. The name is needed only when nested subcircuit definitions are being made.
Subcircuit Calls
General form:
XYYYYYYY N1 <N2 N3 ...> SUBNAM
Examples:
X1 2 4 17 3 1 MULTI
Subcircuits are used in ngspice by specifying pseudoelements beginning with the letter X, followed by the circuit nodes to be used in expanding the subcircuit. If you use parameters, the subcircuit call will be modified (see 2.8.3).
.GLOBAL
General form:
.GLOBAL nodename
Examples:
.GLOBAL gnd vcc
Nodes defined in the .GLOBAL statement are available to all circuit and subcircuit blocks independently from any circuit hierarchy. After parsing the circuit, these nodes are accessible from top level.
.INCLUDE
General form:
.INCLUDE filename
Examples:
.INCLUDE /users/spice/common/bsim3param.mod
Frequently, portions of circuit descriptions will be reused in several input files, particularly with common models and subcircuits. In any ngspice input file, the .INCLUDE line may be used to copy some other file as if that second file appeared in place of the .INCLUDE line in the original file.
There is no restriction on the file name imposed by ngspice beyond those imposed by the local operating system.
.LIB
General form:
.LIB filename libname
Examples:
.LIB /users/spice/common/mosfets.lib mos1
The .LIB statement allows to include library descriptions into the input file. Inside the *.lib file a library libname will be selected. The statements of each library inside the *.lib file are enclosed in .LIB libname <...> .ENDL statements.
If the compatibility mode (16.13) is set to 'ps' by set ngbehavior=ps (17.7) in spinit (16.5) or .spiceinit (16.6), then a simplified syntax .LIB filename is available: a warning is issued and filename is simply included as described in Chapt. 2.6.
.PARAM Parametric netlists
Ngspice allows for the definition of parametric attributes in the netlists. This is an enhancement of the ngspice frontend that adds arithmetic functionality to the circuit description language.
.param line
General form:
.param <ident> = <expr> <ident> = <expr> ...
Examples:
.param pippo=5
.param po=6 pp=7.8 pap={AGAUSS(pippo, 1, 1.67)}
.param pippp={pippo + pp}
.param p={pp}
.param pop='pp+p'
This line assigns numerical values to identifiers. More than one assignment per line is possible using a separating space. Parameter identifier names must begin with an alphabetic character. The other characters must be either alphabetic, a number, or ! # $ % [ ] _ as special characters. The variables time, temper, and hertz (see 5.1.1) are not valid identifier names. Other restrictions on naming conventions apply as well, see 2.8.6.
The .param lines inside subcircuits are copied per call, like any other line. All assignments are executed sequentially through the expanded circuit. Before its first use, a parameter name must have been assigned a value. Expressions defining a parameter should be put within braces {p+p2}, or alternatively within single quotes 'AGAUSS(pippo, 1, 1.67)'. An assignment cannot be selfreferential, something like .param pip = 'pip+3' will not work.
The current ngspice version does not always need quotes or braces in expressions, especially when spaces are used sparingly. However, it is recommended to do so, as the following examples demonstrate.
.param a = 123 * 3 b = sqrt(9) $ doesn't work, a <= 123
.param a = '123 * 3' b = sqrt(9) $ ok.
.param c = a + 123 $ won't work
.param c = 'a + 123' $ ok.
.param c = a+123 $ ok.
Brace expressions in circuit elements:
General form:
{ <expr> }
Examples:
These are allowed in .model lines and in device lines. A SPICE number is a floating point number with an optional scaling suffix, immediately glued to the numeric tokens (see Chapt. 2.8.5). Brace expressions ({..}) cannot be used to parametrize node names or parts of names. All identifiers used within an <expr> must have known values at the time when the line is evaluated, else an error is flagged.
Subcircuit parameters
General form:
.subckt <identn> node node ... <ident>=<value> <ident>=<value> ...
Examples:
.subckt myfilter in out rval=100k cval=100nF
<identn> is the name of the subcircuit given by the user.** node** is an integer number or an identifier, for one of the external nodes. The first <ident>=<value> introduces an optional section of the line. Each <ident> is a formal parameter, and each <value> is either a SPICE number or a brace expression. Inside the .subckt ... .ends context, each formal parameter may be used like any identifier that was defined on a .param control line. The <value> parts are supposed to be default values of the parameters. However, in the current version of , they are not used and each invocation of the subcircuit must supply the _exact_ number of actual parameters.
The syntax of a subcircuit call (invocation) is:
General form:
X<name> node node ... <identn> <ident>=<value> <ident>=<value> ...
Examples:
X1 input output myfilter rval=1k cval=1n
Here <name> is the symbolic name given to that instance of the subcircuit, <identn> is the name of a subcircuit defined beforehand. node node ... is the list of actual nodes where the subcircuit is connected. <value> is either a SPICE number or a brace expression { <expr> } . The sequence of <value> items on the X line must exactly match the number and the order of formal parameters of the subcircuit.
Subcircuit example with parameters:
* Paramexample
.param amplitude= 1V
*
.subckt myfilter in out rval=100k cval=100nF
Ra in p1 {2*rval}
Rb p1 out {2*rval}
C1 p1 0 {2*cval}
Ca in p2 {cval}
Cb p2 out {cval}
R1 p2 0 {rval}
.ends myfilter
*
X1 input output myfilter rval=1k cval=1n
V1 input 0 AC {amplitude}
.end
Symbol scope
All subcircuit and model names are considered global and must be unique. The .param symbols that are defined outside of any .subckt ... .ends section are global. Inside such a section, the pertaining params: symbols and any .param assignments are considered local: they mask any global identical names, until the .ends line is encountered. You cannot reassign to a global number inside a .subckt, a local copy is created instead. Scope nesting works up to a level of 10. For example, if the main circuit calls A that has a formal parameter xx, A calls B that has a param. xx, and B calls C that also has a formal param. xx, there will be three versions of `xx' in the symbol table but only the most local one  belonging to C  is visible.
Syntax of expressions
<expr> ( optional parts within [...] )
An expression may be one of:
<atom> where <atom> is either a spice number or an identifier
<unaryoperator> <atom>
<functionname> ( <expr> [ , <expr> ...] )
<atom> <binaryoperator> <expr>
( <expr> )
As expected, atoms, builtin function calls and stuff within parentheses are evaluated before the other operators. The operators are evaluated following a list of precedence close to the one of the C language. For equal precedence binary ops, evaluation goes left to right. Functions operate on real values only!
Operator

Alias

Precedence

Description



1

unary 


!

1

unary not


**

^

2

power, like pwr

*

3

multiply


/

3

divide


%

3

modulo


\

3

integer divide


+

4

add




4

subtract


==

5

equality


!=

<>

5

nonequal

<=

5

less or equal


>=

5

greater or equal


<

5

less than


>

5

greater than


&&

6

boolean and




7

boolean or


c?x:y

8

ternary operator

The number zero is used to represent boolean False. Any other number represents boolean True. The result of logical operators is 1 or 0. An example input file is shown below:
Example input file with logical operators:
* Logical operators
v1or 1 0 {1  0}
v1and 2 0 {1 && 0}
v1not 3 0 {! 1}
v1mod 4 0 {5 % 3}
v1div 5 0 {5 \ 3}
v0not 6 0 {! 0}
.control
op
print allv
.endc
.end
Builtin function

Notes

sqrt(x)

y = sqrt(x)

sin(x), cos(x), tan(x)


sinh(x), cosh(x), tanh(x)


asin(x), acos(x), atan(x)


asinh(x), acosh(x), atanh(x)


arctan(x)

atan(x), kept for compatibility

exp(x)


ln(x), log(x)


abs(x)


nint(x)

Nearest integer, half integers towards even

int(x)

Nearest integer rounded towards 0

floor(x)

Nearest integer rounded towards ∞

ceil(x)

Nearest integer rounded towards +∞

pow(x,y)

x raised to the power of y (pow from C runtime library)

pwr(x,y)

pow(fabs(x), y)

min(x, y)


max(x, y)


sgn(x)

1.0 for x > 0, 0.0 for x == 0, 1.0 for x < 0

ternary_fcn(x, y, z)

x ? y : z

gauss(nom, rvar, sigma)

nominal value plus variation drawn from Gaussian distribution with mean 0 and standard deviation rvar (relative to nominal), divided by sigma

agauss(nom, avar, sigma)

nominal value plus variation drawn from Gaussian distribution with mean 0 and standard deviation avar (absolute), divided by sigma

unif(nom, rvar)

nominal value plus relative variation (to nominal) uniformly distributed between +/rvar

aunif(nom, avar)

nominal value plus absolute variation uniformly distributed between +/avar

limit(nom, avar)

nominal value +/avar, depending on random number in [1, 1[ being > 0 or < 0

The scaling suffixes (any decorative alphanumeric string may follow):
suffix

value

g

1e9

meg

1e6

k

1e3

m

1e3

u

1e6

n

1e9

p

1e12

f

1e15

Note: there are intentional redundancies in expression syntax, e.g. x^y , x**y and pwr(x,y) all have nearly the same result.
Reserved words
In addition to the above function names and to the verbose operators ( not and or div mod ), other words are reserved and cannot be used as parameter names: or, defined, sqr, sqrt, sin, cos, exp, ln, log, log10, arctan, abs, pwr, time, temper, hertz.
A word of caution on the three ngspice expression parsers
The historical parameter notation using & as the first character of a line as equivalence to .param. is deprecated and will be removed in a coming release.
Confusion may arise in ngspice because of its multiple numerical expression features. The .param lines and the brace expressions (see Chapt. 2.9) are evaluated in the frontend, that is, just after the subcircuit expansion. (Technically, the X lines are kept as comments in the expanded circuit so that the actual parameters can be correctly substituted). Therefore, after the netlist expansion and before the internal data setup, all number attributes in the circuit are known constants. However, there are circuit elements in Spice that accept arithmetic expressions not evaluated at this point, but only later during circuit analysis. These are the arbitrary current and voltage sources (Bsources, 5), as well as E and Gsources and R, L, or Cdevices. The syntactic difference is that `compiletime' expressions are within braces, but `runtime' expressions have no braces. To make things more complicated, the backend ngspice scripting language accepts arithmetic/logic expressions that operate only on its own scalar or vector data sets (17.2). Please see Chapt. 2.13.
It would be desirable to have the same expression syntax, operator and function set, and precedence rules, for the three contexts mentioned above. In the current Numparam implementation, that goal is not achieved.
.FUNC
This keyword defines a function. The syntax of the expression is the same as for a .param (2.8.5).
General form:
.func <ident> { <expr> }
.func <ident> = { <expr> }
Examples:
.func icos(x) {cos(x)  1}
.func f(x,y) {x*y}
.func foo(a,b) = {a + b}
.func will initiate a replacement operation. After reading the input files, and before parameters are evaluated, all occurrences of the icos(x) function will be replaced by cos(x)1. All occurrences of f(x,y) will be replaced by x*y. Function statements may be nested to a depth of t.b.d..
.CSPARAM
Create a constant vector (see 17.8.2) from a parameter in plot (17.3) const.
General form:
.csparam <ident> = <expr>
Examples:
.param pippo=5
.param pp=6
.csparam pippp={pippo + pp}
.param p={pp}
.csparam pap='pp+p'
In the example shown, vectors pippp, and pap are added to the constants that already reside in plot const, having length one and real values. These vectors are generated during circuit parsing and thus cannot be changed later (same as with ordinary parameters). They may be used in ngspice scripts and .control sections (see Chapt. 17).
The use of .csparam is still experimental and has to be tested. A simple usage is shown below.
* test csparam
.param TEMPS = 27
.csparam newt = {3*TEMPS}
.csparam mytemp = '2 + TEMPS'
.control
echo $&newt $&mytemp
.endc
.end
.TEMP
Sets the circuit temperature in degrees Celsius.
General form:
.temp value
Examples:
.temp 27
This card overrides the circuit temperature given in an .option line (15.1.1).
.IF ConditionControlled Netlist
A simple .IF.ELSE(IF) block allows conditioncontrolling of the netlist. boolean expression is any expression according to Chapt. 2.8.5 that evaluates parameters and returns a boolean 1 or 0. The netlist block in between the .if ... .endif statements may contain device instances or .model cards that are selected according to the logic condition.
General form:
.if(boolean expression)
...
.elseif(boolean expression)
...
.else
...
.endif
Example 1:
* device instance in IFELSE block
.param ok=0 ok2=1
v1 1 0 1
R1 1 0 2
.if (ok && ok2)
R11 1 0 2
.else
R11 1 0 0.5 $ < selected
.endif
Example 2:
* .model in IFELSE block
.param m0=0 m1=1
M1 1 2 3 4 N1 W=1 L=0.5
.if(m0==1)
.model N1 NMOS level=49 Version=3.1
.elseif(m1==1)
.model N1 NMOS level=49 Version=3.2.4 $ < selected
.else
.model N1 NMOS level=49 Version=3.3.0
.endif
Nesting of .IF.ELSE(IF).ENDIF blocks is possible. Several .elseif are allowed per block, of course only one .else (please see example ngspice/tests/regression/misc/ifelseif.cir). However some restrictions apply, as the following netlist components are not supported within the .IF.ENDIF block: .SUBCKT, .INC, .LIB, and .PARAM.
Parameters, functions, expressions, and command scripts
In ngspice there are several ways to describe functional dependencies. In fact there are three independent function parsers, being active before, during, and after the simulation. So it might be due to have a few words on their interdependence.
Parameters
Parameters (Chapt. 2.8.1) and functions, either defined within the .param statement or with the .func statement (Chapt. 2.9) are evaluated before any simulation is started, that is during the setup of the input and the circuit. Therefore these statements may not contain any simulation output (voltage or current vectors), because it is simply not yet available. The syntax is described in Chapt. 2.8.5. During the circuit setup all functions are evaluated, all parameters are replaced by their resulting numerical values. Thus it will not be possible to get feedback from a later stage (during or after simulation) to change any of the parameters.
Nonlinear sources
During the simulation, the B source (Chapt. 5) and their associated E and G sources, as well as some devices (R, C, L) may contain expressions. These expressions may contain parameters from above (evaluated immediately upon ngspice start up), numerical data, predefined functions, but also node voltages and branch currents resulting from the simulation. The source or device values are continuously updated during the simulation. Therefore the sources are powerful tools to define nonlinear behavior, you may even create new `devices' by yourself. Unfortunately the expression syntax (see Chapt. 5.1) and the predefined functions may deviate from the ones for parameters listed in 2.8.1.
Control commands, Command scripts
Commands, as described in detail in Chapt. 17.5, may be used interactively, but also as a command script enclosed in .control ... .endc lines. The scripts may contain expressions (see Chapt. 17.2). The expressions may work upon simulation output vectors (of node voltages, branch currents), as well as upon predefined or user defined vectors and variables, and are invoked after the simulation. Parameters from 2.8.1 defined by the .param statement are not allowed in these expressions. However you may define such parameters with .csparam (2.10). Again the expression syntax (see Chapt. 17.2) will deviate from the one for parameters or B sources listed in 2.8.1 and 5.1.
If you want to use parameters from 2.8.1 inside your control script, you may use .csparam (2.10) or apply a trick by defining a voltage source with the parameter as its value, and then have it available as a vector (e.g. after a transient simulation) with a then constant output (the parameter). A feedback from here back into parameters (2.13.1) is never possible. Also you cannot access nonlinear sources of the preceding simulation. However you may start a first simulation inside your control script, then evaluate its output using expressions, change some of the element or model parameters with the alter and altermod statements (see Chapt. 17.5.3) and then automatically start a new simulation.
Expressions and scripting are powerful tools within ngspice, and we will enhance the examples given in Chapt. 21 continuously to describe these features.
Circuit Elements and Models
Data fields that are enclosed in lessthan and greaterthan signs (`< >') are optional. All indicated punctuation (parentheses, equal signs, etc.) is optional but indicate the presence of any delimiter. Further, future implementations may require the punctuation as stated. A consistent style adhering to the punctuation shown here makes the input easier to understand. With respect to branch voltages and currents, ngspice uniformly uses the associated reference convention (current flows in the direction of voltage drop).
General options and information
Paralleling devices with multiplier m
When it is needed to simulate several devices of the same kind in parallel, use the `m' (parallel multiplier) instance parameter available for the devices listed in Table 3.1. This multiplies the value of the element's matrix stamp with m's value. The netlist below shows how to correctly use the parallel multiplier:
Multiple device example:
d1 2 0 mydiode m=10
d01 1 0 mydiode
d02 1 0 mydiode
d03 1 0 mydiode
d04 1 0 mydiode
d05 1 0 mydiode
d06 1 0 mydiode
d07 1 0 mydiode
d08 1 0 mydiode
d09 1 0 mydiode
d10 1 0 mydiode
...
The d1 instance connected between nodes 2 and 0 is equivalent to the 10 parallel devices d01d10 connected between nodes 1 and 0.
The following devices support the multiplier m:
First letter

Element description

C

Capacitor

D

Diode

F

Currentcontrolled current source (CCCs)

G

Voltagecontrolled current source (VCCS)

I

Current source

J

Junction field effect transistor (JFET)

L

Inductor

M

Metal oxide field effect transistor (MOSFET)

Q

Bipolar junction transistor (BJT)

R

Resistor

X

Subcircuit (for details see below)

Z

Metal semiconductor field effect transistor (MESFET)

Table 3.1: ngspice elements supporting multiplier 'm'
When the X line (e.g. x1 a b sub1 m=5) contains the token m=value (as shown) or m=expression, subcircuit invocation is done in a special way. If an instance line of the subcircuit sub1 contains any of the elements shown in table 3.1, then these elements are instantiated with the additional parameter m (in this example having the value 5). If such an element already has an m multiplier parameter, the element m is multiplied with the m derived from the X line. This works recursively, meaning that if a subcircuit contains another subcircuit (a nested X line), then the latter m parameter will be multiplied by the former one, and so on.
Example 1:
.param madd = 6
X1 a b sub1 m=5
.subckt sub1 a1 b1
Cs1 a1 b1 C=5p m='madd2'
.ends
In example 1, the capacitance between nodes a and b will be C = 5pF*(madd2)*5 = 100pF.
Example 2:
.param madd = 4
X1 a b sub1 m=3
.subckt sub1 a1 b1
X2 a1 b1 sub2 m='madd2'
.ends
.subckt sub2 a2 b2
Cs2 a2 b2 3p m=2
.ends
In example 2, the capacitance between nodes a and b is C = 3pF*2*(madd2)*3 = 36pF.
Using m may fail to correctly describe geometrical properties for real devices like MOS transistors.
M1 d g s nmos W=0.3u L=0.18u m=20
is probably not be the same as
M1 d g s nmos W=6u L=0.18u
because the former may suffer from small width (or edge) effects, whereas the latter is simply a wide transistor.
Instance and model parameters
The simple device example below consists of two lines: The device is defined on the instance line, starting with Lload ...: The first letter determines the device type (an inductor in this example). Following the device name are two nodes 1 and 2, then the inductance value 1u is set. The model name ind1 is a connection to the respective model line. Finally we have a parameter on the instance line, together with its value dtemp=5. Parameters on an instance line are called instance parameters.
The model line starts with the token .model, followed by the model name, the model type and at leat one model parameter, here tc1=0.001. There are complex models with more than 100 model parameters.
Lload 1 2 1u ind1 dtemp=5
.MODEL ind1 L tc1=0.001
Instance parameters are listed in each of the following device descriptions. Model parameters sometimes are given below as well, for complex models like the BSIM transistor models, they are available in the model makers documentation. Instance parameters may also be placed in the .model line. Thus they are reckognized by each device instance referring to that model. Their values may be overridden for a specific instance of a device by placing them additionally onto its instance line.
Model binning
Binning is a kind of range partitioning for geometry dependent models like MOSFET's. The purpose is to cover larger geometry ranges (Width and Length) with higher accuracy then the model builtin geometry formulas. Each size range described by the additional model parameters LMIN, LMAX, WMIN and WMAX has its own model parameter set. These model cards are defined by a number extension, like `nch.1'. NGSPICE has a algorithm to choose the right model card by the requested W and L.
This is implemented for BSIM3 (11.2.10) and BSIM4 (11.2.11) models.
Initial conditions
Two different forms of initial conditions may be specified for some devices. The first form is included to improve the dc convergence for circuits that contain more than one stable state. If a device is specified OFF, the dc operating point is determined with the terminal voltages for that device set to zero. After convergence is obtained, the program continues to iterate to obtain the exact value for the terminal voltages. If a circuit has more than one dc stable state, the OFF option can be used to force the solution to correspond to a desired state. If a device is specified OFF when in reality the device is conducting, the program still obtains the correct solution (assuming the solutions converge) but more iterations are required since the program must independently converge to two separate solutions.
The .NODESET control line (see Chapt. 15.2.1) serves a similar purpose as the OFF option. The .NODESET option is easier to apply and is the preferred means to aid convergence. The second form of initial conditions are specified for use with the transient analysis. These are true `initial conditions' as opposed to the convergence aids above. See the description of the .IC control line (Chapt. 15.2.2) and the .TRAN control line (Chapt. 15.3.9) for a detailed explanation of initial conditions.
Elementary Devices
Resistors
General form:
RXXXXXXX n+ n <resistancer=>value <ac=val> <m=val>
+ <scale=val> <temp=val> <dtemp=val> <tc1=val> <tc2=val>
+ <noisy=01>
Examples:
R1 1 2 100
RC1 12 17 1K
R2 5 7 1K ac=2K
RL 1 4 2K m=2
Ngspice has a fairly complex model for resistors. It can simulate both discrete and semiconductor resistors. Semiconductor resistors in ngspice means: resistors described by geometrical parameters. So, do not expect detailed modeling of semiconductor effects.
n+ and n are the two element nodes, value is the resistance (in ohms) and may be positive or negative
1
A negative resistor modeling an active element can cause convergence problems, please avoid it.
but not zero.
Simulating small valued resistors: If you need to simulate very small resistors (0.001 Ohm or less), you should use CCVS (transresistance), it is less efficient but improves overall numerical accuracy. Think about that a small resistance is a large conductance.
Ngspice can assign a resistor instance a different value for AC analysis, specified using the ac keyword. This value must not be zero as described above. The AC resistance is used in AC analysis only (neither PoleZero nor Noise). If you do not specify the ac parameter, it is defaulted to value.
Ngspice calculates the nominal resistance as
[\begin{array}{ll} \begin{array}{ll} {R_{nom} =} & \frac{{\lbrack font\ rm\ \lbrack char\ V\ mathalpha\rbrack\lbrack char\ A\ mathalpha\rbrack\lbrack char\ L\ mathalpha\rbrack\lbrack char\ U\ mathalpha\rbrack\lbrack char\ E\ mathalpha\rbrack\rbrack}{\lbrack font\ rm\ \lbrack char\ s\ mathalpha\rbrack\lbrack char\ c\ mathalpha\rbrack\lbrack char\ a\ mathalpha\rbrack\lbrack char\ l\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack}}{m} \ & \ {R_{acnom} =} & {\frac{{\lbrack font\ rm\ \lbrack char\ a\ mathalpha\rbrack\lbrack char\ c\ mathalpha\rbrack\rbrack}{\lbrack font\ rm\ \lbrack char\ s\ mathalpha\rbrack\lbrack char\ c\ mathalpha\rbrack\lbrack char\ a\ mathalpha\rbrack\lbrack char\ l\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack}}{m}.} \ \end{array} & \ \end{array}]
If you want to simulate temperature dependence of a resistor, you need to specify its temperature coefficients, using a .model line or as instance parameters, like in the examples below:
Examples:
RE1 1 2 800 newres dtemp=5
.MODEL newres R tc1=0.001
RE2 a b 1.4k tc1=2m tc2=1.4u
RE3 n1 n2 1Meg tce=700m
The temperature coefficients tc1 and tc2 describe a quadratic temperature dependence (see equation 6) of the resistance. If given in the instance line (the R... line) their values will override the tc1 and tc2 of the .model line (3.2.3). Ngspice has an additional temperature model equation 12 parametrized by tce given in model or instance line. If all parameters are given (quadratic and exponential) the exponential temperature model is chosen.
[\begin{array}{ll} {R\left( T \right) = R\left( T_{0} \right)\left\lbrack {1.01^{TCE \cdot ({T  T_{0}})}} \right\rbrack} & \ \end{array}]
where (T) is the circuit temperature, (T_{0}) is the nominal temperature, and (TCE) is the exponential temperature coefficients.
Instance temperature is useful even if resistance does not vary with it, since the thermal noise generated by a resistor depends on its absolute temperature. Resistors in ngspice generates two different noises: thermal and flicker. While thermal noise is always generated in the resistor, to add a flicker noise
2
Flicker noise can be used to model carbon resistors.
source you have to add a .model card defining the flicker noise parameters. It is possible to simulate resistors that do not generate any kind of noise using the noisy (or noise) keyword and assigning zero to it, as in the following example:
Example:
Rmd 134 57 1.5k noisy=0
If you are interested in temperature effects or noise equations, read the next section on semiconductor resistors.
Semiconductor Resistors
General form:
RXXXXXXX n+ n <value> <mname> <l=length> <w=width>
+ <temp=val> <dtemp=val> <m=val> <ac=val> <scale=val>
+ <noisy = 01>
Examples:
RLOAD 2 10 10K
RMOD 3 7 RMODEL L=10u W=1u
This is the more general form of the resistor presented before (3.2.1) and allows the modeling of temperature effects and for the calculation of the actual resistance value from strictly geometric information and the specifications of the process. If value is specified, it overrides the geometric information and defines the resistance. If mname is specified, then the resistance may be calculated from the process information in the model** mname** and the given length and width. If value is not specified, then mname and length must be specified. If width is not specified, then it is taken from the default width given in the model.
The (optional) temp value is the temperature at which this device is to operate, and overrides the temperature specification on the .option control line and the value specified in dtemp.
Semiconductor Resistor Model (R)
The resistor model consists of processrelated device data that allow the resistance to be calculated from geometric information and to be corrected for temperature. The parameters available are:
Name

Parameter

Units

Default

Example

TC1

first order temperature coeff.

$\frac{\Omega}{C}$

0.0



TC2

second order temperature coeff.

$\frac{\Omega}{C^{2}}$

0.0



RSH

sheet resistance

$\frac{\Omega}{\square}$



50

DEFW

default width

m

1e6

2e6

NARROW

narrowing due to side etching

m

0.0

1e7

SHORT

shortening due to side etching

m

0.0

1e7

TNOM

parameter measurement temperature

C

27

50

KF

flicker noise coefficient

0.0

1e25


AF

flicker noise exponent

0.0

1.0


WF

flicker noise width exponent

1.0


LF

flicker noise length exponent

1.0


EF

flicker noise frequency exponent

1.0


R (RES)

default value if element value not given

Ω



1000

The sheet resistance is used with the narrowing parameter and l and w from the resistor device to determine the nominal resistance by the formula:
[\begin{array}{ll} {R_{nom} = {\lbrack font\ rm\ \lbrack char\ r\ mathalpha\rbrack\lbrack char\ s\ mathalpha\rbrack\lbrack char\ h\ mathalpha\rbrack\rbrack}\frac{l  {\lbrack font\ rm\ \lbrack char\ S\ mathalpha\rbrack\lbrack char\ H\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ R\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\rbrack}}{w  {\lbrack font\ rm\ \lbrack char\ N\ mathalpha\rbrack\lbrack char\ A\ mathalpha\rbrack\lbrack char\ R\ mathalpha\rbrack\lbrack char\ R\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ W\ mathalpha\rbrack\rbrack}}} & \ \end{array}]
DEFW is used to supply a default value for w if one is not specified for the device. If either rsh or l is not specified, then the standard default resistance value of 1 mOhm is used. TNOM is used to override the circuitwide value given on the .options control line where the parameters of this model have been measured at a different temperature. After the nominal resistance is calculated, it is adjusted for temperature by the formula:
[\begin{array}{ll} {R\left( T \right) = R\left( {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right)\left( 1 + TC_{1}\left( {T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack}} \right) + TC_{2}\left( T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack})^{2} \right) \right.} & \ \end{array}]
where (R\left( {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right) = R_{nom}R_{acnom}). In the above formula, `(T)' represents the instance temperature, which can be explicitly set using the temp keyword or calculated using the circuit temperature and dtemp, if present. If both temp and dtemp are specified, the latter is ignored. Ngspice improves SPICE's resistors noise model, adding flicker noise ((\frac{1}{f})) to it and the noisy (or noise) keyword to simulate noiseless resistors. The thermal noise in resistors is modeled according to the equation:
[\begin{array}{ll} {\bar{i_{R}^{2}} = \frac{4kT}{R}\Delta f} & \ \end{array}]
where `(k)' is the Boltzmann's constant, and `(T)' the instance temperature.
Flicker noise model is:
[\begin{array}{ll} {\bar{i_{Rfn}^{2}} = \frac{{\lbrack font\ rm\ \lbrack char\ K\ mathalpha\rbrack\lbrack char\ F\ mathalpha\rbrack\rbrack}I_{R}^{\lbrack font\ rm\ \lbrack char\ A\ mathalpha\rbrack\lbrack char\ F\ mathalpha\rbrack\rbrack}}{W^{WF}L^{LF}f^{EF}}\Delta f} & \ \end{array}]
A small list of sheet resistances (in (\frac{\Omega}{\square})) for conductors is shown below. The table represents typical values for MOS processes in the 0.5  1 um
range. The table is taken from: N. Weste, K. Eshraghian  Principles of CMOS VLSI Design 2nd Edition, Addison Wesley.
Material

Min.

Typ.

Max.

Intermetal (metal1  metal2)

0.005

0.007

0.1

Topmetal (metal3)

0.003

0.004

0.05

Polysilicon (poly)

15

20

30

Silicide

2

3

6

Diffusion (n+, p+)

10

25

100

Silicided diffusion

2

4

10

nwell

1000

2000

5000

Resistors, dependent on expressions (behavioral resistor)
General form:
RXXXXXXX n+ n R = 'expression' <tc1=value> <tc2=value> <noisy=0>
RXXXXXXX n+ n 'expression' <tc1=value> <tc2=value> <noisy=0>
Examples:
R1 rr 0 r = 'V(rr) < {Vt} ? {R0} : {2*R0}' tc1=2e03 tc2=3.3e06
R2 r2 rr r = {5k + 50*TEMPER}
.param rp1 = 20
R3 no1 no2 r = '5k * rp1' noisy=1
Expression may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in Chapt. 5.1. It may contain parameters (2.8.1) and the special variables time, temper, and hertz (5.1.2). An example file is given below. Small signal noise in the resistor (15.3.4) may be evaluated as white noise, depending on resistance, temperature and tc1, tc2. To enable noise calculation, add the flag noisy=1 to the instance line. As a default the behavioral resistor is noiseless.
Example input file for nonlinear resistor:
Nonlinear resistor
.param R0=1k Vi=1 Vt=0.5
* resistor depending on control voltage V(rr)
R1 rr 0 r = 'V(rr) < {Vt} ? {R0} : {2*R0}'
* control voltage
V1 rr 0 PWL(0 0 100u {Vi})
.control
unset askquit
tran 100n 100u uic
plot i(V1)
.endc
.end
Capacitors
General form:
CXXXXXXX n+ n <value> <mname> <m=val> <scale=val> <temp=val>
+ <dtemp=val> <tc1=val> <tc2=val> <ic=init_condition>
Examples:
CBYP 13 0 1UF
COSC 17 23 10U IC=3V
Ngspice provides a detailed model for capacitors. Capacitors in the netlist can be specified giving their capacitance or their geometrical and physical characteristics. Following the original SPICE3 `convention', capacitors specified by their geometrical or physical characteristics are called `semiconductor capacitors' and are described in the next section.
In this first form n+ and n are the positive and negative element nodes, respectively and value is the capacitance in Farads.
Capacitance can be specified in the instance line as in the examples above or in a .model line, as in the example below:
C1 15 5 cstd
C2 2 7 cstd
.model cstd C cap=3n
Both capacitors have a capacitance of 3nF.
If you want to simulate temperature dependence of a capacitor, you need to specify its temperature coefficients, using a .model line, like in the example below:
CEB 1 2 1u cap1 dtemp=5
.MODEL cap1 C tc1=0.001
The (optional) initial condition is the initial (time zero) value of capacitor voltage (in Volts). Note that the initial conditions (if any) apply only if the uic option is specified on the .tran control line.
Ngspice calculates the nominal capacitance as described below:
[\begin{array}{ll} {C_{nom} = {{{\lbrack font\ rm\ \lbrack char\ v\ mathalpha\rbrack\lbrack char\ a\ mathalpha\rbrack\lbrack char\ l\ mathalpha\rbrack\lbrack char\ u\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack} \cdot {\lbrack font\ rm\ \lbrack char\ s\ mathalpha\rbrack\lbrack char\ c\ mathalpha\rbrack\lbrack char\ a\ mathalpha\rbrack\lbrack char\ l\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack}} \cdot m}} & \ \end{array}]
The temperature coefficients tc1 and tc2 describe a quadratic temperature dependence (see equation77) of the capacitance. If given in the instance line (the C... line) their values will override the tc1 and tc2 of the .model line (3.2.7).
Semiconductor Capacitors
General form:
CXXXXXXX n+ n <value> <mname> <l=length> <w=width> <m=val>
+ <scale=val> <temp=val> <dtemp=val> <ic=init_condition>
Examples:
CLOAD 2 10 10P
CMOD 3 7 CMODEL L=10u W=1u
This is the more general form of the Capacitor presented in section (3.2.5), and allows for the calculation of the actual capacitance value from strictly geometric information and the specifications of the process. If value is specified, it defines the capacitance and both process and geometrical information are discarded. If value is not specified, the capacitance is calculated from information contained model mname and the given length and width (l, w keywords, respectively).
It is possible to specify mname only, without geometrical dimensions and set the capacitance in the .model line (3.2.5).
Semiconductor Capacitor Model (C)
The capacitor model contains process information that may be used to compute the capacitance from strictly geometric information.
Name

Parameter

Units

Default

Example

CAP

model capacitance

F

0.0

1e6

CJ

junction bottom capacitance

$\frac{F}{m^{2}}$



5e5

CJSW

junction sidewall capacitance

$\frac{F}{m}$



2e11

DEFW

default device width

m

1e6

2e6

DEFL

default device length

m

0.0

1e6

NARROW

narrowing due to side etching

m

0.0

1e7

SHORT

shortening due to side etching

m

0.0

1e7

TC1

first order temperature coeff.

$\frac{F}{C}$

0.0

0.001

TC2

second order temperature coeff.

$\frac{F}{C^{2}}$

0.0

0.0001

TNOM

parameter measurement temperature

C

27

50

DI

relative dielectric constant

$\frac{F}{m}$



1

THICK

insulator thickness

m

0.0

1e9

The capacitor has a capacitance computed as:
If value is specified on the instance line then
[\begin{array}{ll} {C_{nom} = {{{\lbrack font\ rm\ \lbrack char\ v\ mathalpha\rbrack\lbrack char\ a\ mathalpha\rbrack\lbrack char\ l\ mathalpha\rbrack\lbrack char\ u\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack} \cdot {\lbrack font\ rm\ \lbrack char\ s\ mathalpha\rbrack\lbrack char\ c\ mathalpha\rbrack\lbrack char\ a\ mathalpha\rbrack\lbrack char\ l\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack}} \cdot m}} & \ \end{array}]
If model capacitance is specified then
[\begin{array}{ll} {C_{nom} = {{{\lbrack font\ rm\ \lbrack char\ C\ mathalpha\rbrack\lbrack char\ A\ mathalpha\rbrack\lbrack char\ P\ mathalpha\rbrack\rbrack} \cdot {\lbrack font\ rm\ \lbrack char\ s\ mathalpha\rbrack\lbrack char\ c\ mathalpha\rbrack\lbrack char\ a\ mathalpha\rbrack\lbrack char\ l\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack}} \cdot m}} & \ \end{array}]
If neither value nor CAP are specified, then geometrical and physical parameters are take into account:
[\begin{array}{ll} {{\lbrack font\ rm\ \lbrack sub\ \lbrack char\ C\ mathalpha\rbrack\ \lbrack char\ 0\ mathalpha\rbrack\rbrack\rbrack} = {\lbrack font\ rm\ \lbrack char\ C\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack}\left( {l  {\lbrack font\ rm\ \lbrack char\ S\ mathalpha\rbrack\lbrack char\ H\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ R\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\rbrack}} \right)\left( {w  {\lbrack font\ rm\ \lbrack char\ N\ mathalpha\rbrack\lbrack char\ A\ mathalpha\rbrack\lbrack char\ R\ mathalpha\rbrack\lbrack char\ R\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ W\ mathalpha\rbrack\rbrack}} \right) + 2{\lbrack font\ rm\ \lbrack char\ C\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\lbrack char\ W\ mathalpha\rbrack\rbrack}\left( {l  {\lbrack font\ rm\ \lbrack char\ S\ mathalpha\rbrack\lbrack char\ H\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ R\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\rbrack} + w  {\lbrack font\ rm\ \lbrack char\ N\ mathalpha\rbrack\lbrack char\ A\ mathalpha\rbrack\lbrack char\ R\ mathalpha\rbrack\lbrack char\ R\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ W\ mathalpha\rbrack\rbrack}} \right)} & \ \end{array}]
CJ can be explicitly given on the .model line or calculated by physical parameters. When CJ is not given, is calculated as:
If THICK is not zero:
[\begin{array}{ll} \begin{array}{ll} {{\lbrack font\ rm\ \lbrack char\ C\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack} = \frac{{\lbrack font\ rm\ \lbrack char\ D\ mathalpha\rbrack\lbrack char\ I\ mathalpha\rbrack\rbrack}\varepsilon_{0}}{\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ H\ mathalpha\rbrack\lbrack char\ I\ mathalpha\rbrack\lbrack char\ C\ mathalpha\rbrack\lbrack char\ K\ mathalpha\rbrack\rbrack}} & {if DI is specified,} \ & \ {{\lbrack font\ rm\ \lbrack char\ C\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack} = \frac{\varepsilon_{SiO_{2}}}{\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ H\ mathalpha\rbrack\lbrack char\ I\ mathalpha\rbrack\lbrack char\ C\ mathalpha\rbrack\lbrack char\ K\ mathalpha\rbrack\rbrack}} & {otherwise.} \ \end{array} & \ \end{array}]
If the relative dielectric constant is not specified the one for SiO2 is used. The values of the constants are: (\varepsilon_{0} = 8.854214871e  12\frac{F}{m}) and (\varepsilon_{SiO_{2}} = 3.4531479969e  11\frac{F}{m}). The nominal capacitance is then computed as:
[\begin{array}{ll} {C_{nom} = {C_{0}{\lbrack font\ rm\ \lbrack char\ s\ mathalpha\rbrack\lbrack char\ c\ mathalpha\rbrack\lbrack char\ a\ mathalpha\rbrack\lbrack char\ l\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack} m}} & \ \end{array}]
After the nominal capacitance is calculated, it is adjusted for temperature by the formula:
[\begin{array}{ll} {C\left( T \right) = C\left( {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right)\left( 1 + TC_{1}\left( {T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack}} \right) + TC_{2}\left( T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack})^{2} \right) \right.} & \ \end{array}]
where (C\left( {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right) = C_{nom}).
In the above formula, `(T)' represents the instance temperature, which can be explicitly set using the temp keyword or calculated using the circuit temperature and dtemp, if present.
Capacitors, dependent on expressions (behavioral capacitor)
General form:
CXXXXXXX n+ n C = 'expression' <tc1=value> <tc2=value>
CXXXXXXX n+ n 'expression' <tc1=value> <tc2=value>
Examples:
C1 cc 0 c = 'V(cc) < {Vt} ? {C1} : {Ch}' tc1=1e03 tc2=1.3e05
Expression may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in Chapt. 5.1. It may contain parameters (2.8.1) and the special variables time, temper, and hertz (5.1.2).
Example input file:
Behavioral Capacitor
.param Cl=5n Ch=1n Vt=1m Il=100n
.ic v(cc) = 0 v(cc2) = 0
* capacitor depending on control voltage V(cc)
C1 cc 0 c = 'V(cc) < {Vt} ? {Cl} : {Ch}'
*C1 cc 0 c ={Ch}
I1 0 1 {Il}
Exxx n1copy n2 n2 cc2 1
Cxxx n1copy n2 1
Bxxx cc2 n2 I = '(V(cc2) < {Vt} ? {Cl} : {Ch})' * i(Exxx)
I2 n2 22 {Il}
vn2 n2 0 DC 0
* measure charge by integrating current
aint1 %id(1 cc) 2 time_count
aint2 %id(22 cc2) 3 time_count
.model time_count int(in_offset=0.0 gain=1.0
+ out_lower_limit=1e12 out_upper_limit=1e12
+ limit_range=1e9 out_ic=0.0)
.control
unset askquit
tran 100n 100u
plot v(2)
plot v(cc) v(cc2)
.endc
.end
Inductors
General form:
LYYYYYYY n+ n <value> <mname> <nt=val> <m=val>
+ <scale=val> <temp=val> <dtemp=val> <tc1=val>
+ <tc2=val> <ic=init_condition>
Examples:
LLINK 42 69 1UH
LSHUNT 23 51 10U IC=15.7MA
The inductor device implemented into ngspice has many enhancements over the original one.n+ and n are the positive and negative element nodes, respectively. value is the inductance in Henry. Inductance can be specified in the instance line as in the examples above or in a .model line, as in the example below:
L1 15 5 indmod1
L2 2 7 indmod1
.model indmod1 L ind=3n
Both inductors have an inductance of 3nH.
The nt is used in conjunction with a .model line, and is used to specify the number of turns of the inductor. If you want to simulate temperature dependence of an inductor, you need to specify its temperature coefficients, using a .model line, like in the example below:
Lload 1 2 1u ind1 dtemp=5
.MODEL ind1 L tc1=0.001
The (optional) initial condition is the initial (time zero) value of inductor current (in Amps) that flows from n+, through the inductor, to n. Note that the initial conditions (if any) apply only if the UIC option is specified on the .tran analysis line.
Ngspice calculates the nominal inductance as described below:
[\begin{array}{ll} {L_{nom} = \frac{{\lbrack font\ rm\ \lbrack char\ v\ mathalpha\rbrack\lbrack char\ a\ mathalpha\rbrack\lbrack char\ l\ mathalpha\rbrack\lbrack char\ u\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack}{\lbrack font\ rm\ \lbrack char\ s\ mathalpha\rbrack\lbrack char\ c\ mathalpha\rbrack\lbrack char\ a\ mathalpha\rbrack\lbrack char\ l\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack}}{m}} & \ \end{array}]
Inductor model
The inductor model contains physical and geometrical information that may be used to compute the inductance of some common topologies like solenoids and toroids, wound in air or other material with constant magnetic permeability.
Name

Parameter

Units

Default

Example

IND

model inductance

H

0.0

1e3

CSECT

cross section

m^{2}

0.0

1e3

LENGTH

length

m

0.0

1e2

TC1

first order temperature coeff.

$\frac{H}{C}$

0.0

0.001

TC2

second order temperature coeff.

$\frac{H}{C^{2}}$

0.0

0.0001

TNOM

parameter measurement temperature

C

27

50

NT

number of turns



0.0

10

MU

relative magnetic permeability

$\frac{H}{m}$

0.0



The inductor has an inductance computed as:
If value is specified on the instance line then
[\begin{array}{ll} {L_{nom} = \frac{{\lbrack font\ rm\ \lbrack char\ v\ mathalpha\rbrack\lbrack char\ a\ mathalpha\rbrack\lbrack char\ l\ mathalpha\rbrack\lbrack char\ u\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack}{\lbrack font\ rm\ \lbrack char\ s\ mathalpha\rbrack\lbrack char\ c\ mathalpha\rbrack\lbrack char\ a\ mathalpha\rbrack\lbrack char\ l\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack}}{m}} & \ \end{array}]
If model inductance is specified then
[\begin{array}{ll} {L_{nom} = \frac{{\lbrack font\ rm\ \lbrack char\ I\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ D\ mathalpha\rbrack\rbrack}{\lbrack font\ rm\ \lbrack char\ s\ mathalpha\rbrack\lbrack char\ c\ mathalpha\rbrack\lbrack char\ a\ mathalpha\rbrack\lbrack char\ l\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack}}{m}} & \ \end{array}]
If neither value nor IND are specified, then geometrical and physical parameters are take into account. In the following formulas
NT refers to both instance and model parameter (instance parameter overrides model parameter):
If LENGTH is not zero:
[\begin{array}{ll} \begin{cases} {L_{nom} = \frac{{\lbrack font\ rm\ \lbrack char\ M\ mathalpha\rbrack\lbrack char\ U\ mathalpha\rbrack\rbrack}\mu_{0}{\lbrack font\ rm\ \lbrack char\ N\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\rbrack}^{2}{\lbrack font\ rm\ \lbrack char\ C\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\lbrack char\ E\ mathalpha\rbrack\lbrack char\ C\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\rbrack}}{\lbrack font\ rm\ \lbrack char\ L\ mathalpha\rbrack\lbrack char\ E\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ G\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\lbrack char\ H\ mathalpha\rbrack\rbrack}} & {{if}{\lbrack font\ rm\ \lbrack char\ M\ mathalpha\rbrack\lbrack char\ U\ mathalpha\rbrack\lbrack mathrm\ \lbrack space\ 6\rbrack\ \lbrack char\ i\ mathalpha\rbrack\lbrack char\ s\ mathalpha\rbrack\lbrack space\ 6\rbrack\ \lbrack char\ s\ mathalpha\rbrack\lbrack char\ p\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\lbrack char\ c\ mathalpha\rbrack\lbrack char\ i\ mathalpha\rbrack\lbrack char\ f\ mathalpha\rbrack\lbrack char\ i\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\lbrack char\ d\ mathalpha\rbrack\lbrack char\ ,\ mathalpha\rbrack\rbrack\rbrack}} \ {L_{nom} = \frac{\mu_{0}{\lbrack font\ rm\ \lbrack char\ N\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\rbrack}^{2}{\lbrack font\ rm\ \lbrack char\ C\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\lbrack char\ E\ mathalpha\rbrack\lbrack char\ C\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\rbrack}}{\lbrack font\ rm\ \lbrack char\ L\ mathalpha\rbrack\lbrack char\ E\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ G\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\lbrack char\ H\ mathalpha\rbrack\rbrack}} & {otherwise.} \ \end{cases} & \ \end{array}]
with (\mu_{0} = 1.25663706143592\frac{\mu H}{m}). After the nominal inductance is calculated, it is adjusted for temperature by the formula
[\begin{array}{ll} {L\left( T \right) = L\left( {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right)\left( 1 + TC_{1}\left( {T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack}} \right) + TC_{2}\left( T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack})^{2} \right), \right.} & \ \end{array}]
where (L\left( {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right) = L_{nom}). In the above formula, `(T)' represents the instance temperature, which can be explicitly set using the temp keyword or calculated using the circuit temperature and dtemp, if present.
Coupled (Mutual) Inductors
General form:
KXXXXXXX LYYYYYYY LZZZZZZZ value
Examples:
K43 LAA LBB 0.999
KXFRMR L1 L2 0.87
LYYYYYYY and LZZZZZZZ are the names of the two coupled inductors, and value is the coefficient of coupling, K, which must be greater than 0 and less than or equal to 1. Using the `dot' convention, place a `dot' on the first node of each inductor.
Inductors, dependent on expressions (behavioral inductor)
General form:
LXXXXXXX n+ n L = 'expression' <tc1=value> <tc2=value>
LXXXXXXX n+ n 'expression' <tc1=value> <tc2=value>
Examples:
L1 l2 lll L = 'i(Vm) < {It} ? {Ll} : {Lh}' tc1=4e03 tc2=6e05
Expression may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in Chapt. 5.1. It may contain parameters (2.8.1) and the special variables time, temper, and hertz (5.1.2).
Example input file:
Variable inductor
.param Ll=0.5m Lh=5m It=50u Vi=2m
.ic v(int21) = 0
* variable inductor depending on control current i(Vm)
L1 l2 lll L = 'i(Vm) < {It} ? {Ll} : {Lh}'
* measure current through inductor
vm lll 0 dc 0
* voltage on inductor
V1 l2 0 {Vi}
* fixed inductor
L3 33 331 {Ll}
* measure current through inductor
vm33 331 0 dc 0
* voltage on inductor
V3 33 0 {Vi}
* non linear inductor (discrete setup)
F21 int21 0 B21 1
L21 int21 0 1
B21 n1 n2 V = '(i(Vm21) < {It} ? {Ll} : {Lh})' * v(int21)
* measure current through inductor
vm21 n2 0 dc 0
V21 n1 0 {Vi}
.control
unset askquit
tran 1u 100u uic
plot i(Vm) i(vm33)
plot i(vm21) i(vm33)
plot i(vm)i(vm21)
.endc
.end
Capacitor or inductor with initial conditions
The simulator supports the specification of voltage and current initial conditions on capacitor and inductor models, respectively. These models are not the standard ones supplied with SPICE3, but are in fact code models that can be substituted for the SPICE models when realistic initial conditions are required. For details please refer to Chapter 12. A XSPICE deck example using these models is shown below:
*
* This circuit contains a capacitor and an inductor with
* initial conditions on them. Each of the components
* has a parallel resistor so that an exponential decay
* of the initial condition occurs with a time constant of
* 1 second.
*
a1 1 0 cap
.model cap capacitor (c=1000uf ic=1)
r1 1 0 1k
*
a2 2 0 ind
.model ind inductor (l=1H ic=1)
r2 2 0 1.0
*
.control
tran 0.01 3
plot v(1) v(2)
.endc
.end
Switches
Two types of switches are available: a voltage controlled switch (type SXXXXXX, model SW) and a current controlled switch (type WXXXXXXX, model CSW). A switching hysteresis may be defined, as well as on and offresistances ((\left. 0 < R < \infty \right)).
General form:
SXXXXXXX N+ N NC+ NC MODEL <ON><OFF>
WYYYYYYY N+ N VNAM MODEL <ON><OFF>
Examples:
s1 1 2 3 4 switch1 ON
s2 5 6 3 0 sm2 off
Switch1 1 2 10 0 smodel1
w1 1 2 vclock switchmod1
W2 3 0 vramp sm1 ON
wreset 5 6 vclck lossyswitch OFF
Nodes 1 and 2 are the nodes between which the switch terminals are connected. The model name is mandatory while the initial conditions are optional. For the voltage controlled switch, nodes 3 and 4 are the positive and negative controlling nodes respectively. For the current controlled switch, the controlling current is that through the specified voltage source. The direction of positive controlling current flow is from the positive node, through the source, to the negative node.
The instance parameters ON or OFF are required, when the controlling voltage (current) starts inside the range of the hysteresis loop (different outputs during forward vs. backward voltage or current ramp). Then ON or OFF determine the initial state of the switch.
Switch Model (SW/CSW)
The switch model allows an almost ideal switch to be described in ngspice. The switch is not quite ideal, in that the resistance can not change from 0 to infinity, but must always have a finite positive value. By proper selection of the on and off resistances, they can be effectively zero and infinity in comparison to other circuit elements. The parameters available are:
Name

Parameter

Units

Default

Switch model

VT

threshold voltage

V

0.0

SW

IT

threshold current

A

0.0

CSW

VH

hysteresis voltage

V

0.0

SW

IH

hysteresis current

A

0.0

CSW

RON

on resistance

Ω

1.0

SW,CSW

ROFF

off resistance

Ω

1.0e+12 (*)

SW,CSW

(*) Or (1/GMIN), if you have set (GMIN) to any other value, see the .OPTIONS control line (15.1.2) for a description of (GMIN), its default value results in an offresistance of 1.0e+12 ohms.
The use of an ideal element that is highly nonlinear such as a switch can cause large discontinuities to occur in the circuit node voltages. A rapid change such as that associated with a switch changing state can cause numerical roundoff or tolerance problems leading to erroneous results or time step difficulties. The user of switches can improve the situation by taking the following steps:
 First, it is wise to set the ideal switch impedance just high or low enough to be negligible with respect to other circuit elements. Using switch impedances that are close to `ideal' in all cases aggravates the problem of discontinuities mentioned above. Of course, when modeling real devices such as MOSFETS, the on resistance should be adjusted to a realistic level depending on the size of the device being modeled.
 If a wide range of ON to OFF resistance must be used in the switches (ROFF/RON > 1e+12), then the tolerance on errors allowed during transient analysis should be decreased by using the .OPTIONS control line and specifying TRTOL to be less than the default value of 7.0.
 When switches are placed around capacitors, then the option CHGTOL should also be reduced. Suggested values for these two options are 1.0 and 1e16 respectively. These changes inform ngspice to be more careful around the switch points so that no errors are made due to the rapid change in the circuit.
Example input file:
Switch test
.tran 2us 5ms
*switch control voltage
v1 1 0 DC 0.0 PWL(0 0 2e3 2 4e3 0)
*switch control voltage starting inside hysteresis window
*please note influence of instance parameters ON, OFF
v2 2 0 DC 0.0 PWL(0 0.9 2e3 2 4e3 0.4)
*switch control current
i3 3 0 DC 0.0 PWL(0 0 2e3 2m 4e3 0) $ < switch control current
*load voltage
v4 4 0 DC 2.0
*input load for current source i3
r3 3 33 10k
vm3 33 0 dc 0 $ < measure the current
* ouput load resistors
r10 4 10 10k
r20 4 20 10k
r30 4 30 10k
r40 4 40 10k
*
s1 10 0 1 0 switch1 OFF
s2 20 0 2 0 switch1 OFF
s3 30 0 2 0 switch1 ON
.model switch1 sw vt=1 vh=0.2 ron=1 roff=10k
*
w1 40 0 vm3 wswitch1 off
.model wswitch1 csw it=1m ih=0.2m ron=1 roff=10k
*
.control
run
plot v(1) v(10)
plot v(10) vs v(1) $ < get hysteresis loop
plot v(2) v(20) $ < different initial values
plot v(20) vs v(2) $ < get hysteresis loop
plot v(2) v(30) $ < different initial values
plot v(30) vs v(2) $ < get hysteresis loop
plot v(40) vs vm3#branch $ < current controlled switch hysteresis
.endc
.end
Voltage and Current Sources
Independent Sources for Voltage or Current
General form:
VXXXXXXX N+ N <<DC> DC/TRAN VALUE> <AC <ACMAG <ACPHASE>>>
+ <DISTOF1 <F1MAG <F1PHASE>>> <DISTOF2 <F2MAG <F2PHASE>>>
IYYYYYYY N+ N <<DC> DC/TRAN VALUE> <AC <ACMAG <ACPHASE>>>
+ <DISTOF1 <F1MAG <F1PHASE>>> <DISTOF2 <F2MAG <F2PHASE>>>
Examples:
VCC 10 0 DC 6
VIN 13 2 0.001 AC 1 SIN(0 1 1MEG)
ISRC 23 21 AC 0.333 45.0 SFFM(0 1 10K 5 1K)
VMEAS 12 9
VCARRIER 1 0 DISTOF1 0.1 90.0
VMODULATOR 2 0 DISTOF2 0.01
IIN1 1 5 AC 1 DISTOF1 DISTOF2 0.001
n+ and n are the positive and negative nodes, respectively. Note that voltage sources need not be grounded. Positive current is assumed to flow from the positive node, through the source, to the negative node. A current source of positive value forces current to flow out of the n+ node, through the source, and into the n node. Voltage sources, in addition to being used for circuit excitation, are the `ammeters' for ngspice, that is, zero valued voltage sources may be inserted into the circuit for the purpose of measuring current. They of course have no effect on circuit operation since they represent shortcircuits.
DC/TRAN is the dc and transient analysis value of the source. If the source value is zero both for dc and transient analyses, this value may be omitted. If the source value is timeinvariant (e.g., a power supply), then the value may optionally be preceded by the letters DC.
ACMAG is the ac magnitude and ACPHASE is the ac phase. The source is set to this value in the ac analysis. If ACMAG is omitted following the keyword AC, a value of unity is assumed. If ACPHASE is omitted, a value of zero is assumed. If the source is not an ac smallsignal input, the keyword AC and the ac values are omitted.
DISTOF1 and DISTOF2 are the keywords that specify that the independent source has distortion inputs at the frequencies F1 and F2 respectively (see the description of the .DISTO control line). The keywords may be followed by an optional magnitude and phase. The default values of the magnitude and phase are 1.0 and 0.0 respectively.
Any independent source can be assigned a timedependent value for transient analysis. If a source is assigned a timedependent value, the timezero value is used for dc analysis. There are nine independent source functions:
 pulse,
 exponential,
 sinusoidal,
 piecewise linear,
 singlefrequency FM
 AM
 transient noise
 random voltages or currents
 and external data (only with ngspice shared library).
If parameters other than source values are omitted or set to zero, the default values shown are assumed. TSTEP is the printing increment and TSTOP is the final time – see the .TRAN control line for an explanation.
Pulse
General form (the PHASE parameter is only possible when XSPICE is enabled):
PULSE(V1 V2 TD TR TF PW PER PHASE)
Examples:
VIN 3 0 PULSE(1 1 2NS 2NS 2NS 50NS 100NS)
Name

Parameter

Default Value

Units

V1

Initial value



V, A

V2

Pulsed value



V, A

TD

Delay time

0.0

sec

TR

Rise time

TSTEP

sec

TF

Fall time

TSTEP

sec

PW

Pulse width

TSTOP

sec

PER

Period

TSTOP

sec

PHASE

Phase

0.0

degrees

A single pulse, without phase offset, is described by the following table:
Time

Value

0

V1

TD

V1

TD+TR

V2

TD+TR+PW

V2

TD+TR+PW+TF

V1

TSTOP

V1

Intermediate points are determined by linear interpolation.
Sinusoidal
General form (the PHASE parameter is only possible when XSPICE is enabled):
SIN(VO VA FREQ TD THETA PHASE)
Examples:
VIN 3 0 SIN(0 1 100MEG 1NS 1E10)
Name

Parameter

Default Value

Units

VO

Offset



V, A

VA

Amplitude



V, A

FREQ

Frequency

$\frac{1}{TSTOP}$

Hz

TD

Delay

0.0

sec

THETA

Damping factor

0.0

$\frac{1}{sec}$

PHASE

Phase

0.0

degrees

The shape of the waveform is described by the following formula:
[\begin{array}{ll} {V\left( t \right) = \begin{cases} {V0} & {{if 0 \leq t} < TD} \ {V0 + VA e^{ ({t  TD})THETA}\sin\left( {2\pi \cdot FREQ \cdot \left( {t  TD} \right) + PHASE} \right)} & {{if} TD \leq t < TSTOP.} \ \end{cases}} & \ \end{array}]
Exponential
General Form:
EXP(V1 V2 TD1 TAU1 TD2 TAU2)
Examples:
VIN 3 0 EXP(4 1 2NS 30NS 60NS 40NS)
Name

Parameter

Default Value

Units

V1

Initial value



V, A

V2

pulsed value



V, A

TD1

rise delay time

0.0

sec

TAU1

rise time constant

TSTEP

sec

TD2

fall delay time

TD1+TSTEP

sec

TAU2

fall time constant

TSTEP

sec

The shape of the waveform is described by the following formula:
Let (V21 = V2  V1, V12 = V1  V2):
[\begin{array}{ll} {V\left( t \right) = \begin{cases} {V1} & {{if} 0 \leq t < TD1,} \ {V1 + V21\left( {1  e^{ \frac{({t  TD1})}{TAU1}}} \right)} & {{if} TD1 \leq t < TD2,} \ {V1 + V21\left( {1  e^{ \frac{({t  TD1})}{TAU1}}} \right) + V12\left( {1  e^{ \frac{({t  TD2})}{TAU2}}} \right)} & {{if} TD2 \leq t < TSTOP.} \ \end{cases}} & \ \end{array}]
PieceWise Linear
General Form:
PWL(T1 V1 <T2 V2 T3 V3 T4 V4 ...>) <r=value> <td=value>
Examples:
VCLOCK 7 5 PWL(0 7 10NS 7 11NS 3 17NS 3 18NS 7 50NS 7)
+ r=0 td=15NS
Each pair of values ((T_{i}), (V_{i})) specifies that the value of the source is (V_{i}) (in Volts or Amps) at time = (T_{i}). The value of the source at intermediate values of time is determined by using linear interpolation on the input values. The parameter r determines a repeat time point. If r is not given, the whole sequence of values ((T_{i}), (V_{i})) is issued once, then the output stays at its final value. If r = 0, the whole sequence from time 0 to time Tn is repeated forever. If r = 10ns, the sequence between 10ns and 50ns is repeated forever. the r value has to be one of the time points T1 to Tn of the PWL sequence. If td is given, the whole PWL sequence is delayed by the value of td. Please note that for now r and td are available only with the voltage source, not with the current source.
SingleFrequency FM
General Form (the PHASE parameters are only possible when XSPICE is enabled):
SFFM(VO VA FC MDI FS PHASEC PHASES)
Examples:
V1 12 0 SFFM(0 1M 20K 5 1K)
Name

Parameter

Default value

Units

VO

Offset



V, A

VA

Amplitude



V, A

FC

Carrier frequency

$\frac{1}{TSTOP}$

Hz

MDI

Modulation index




FS

Signal frequency

$\frac{1}{TSTOP}$

Hz

PHASEC

carrier phase

0

degrees

PHASES

signal phase

0

degrees

The shape of the waveform is described by the following equation:
[\begin{array}{ll} {V\left( t \right) = V_{O} + V_{A}\sin\left( {2\pi \cdot FC \cdot t + MDI\sin\left( {2\pi \cdot FS \cdot t + PHASES} \right) + PHASEC} \right)} & \ \end{array}]
Amplitude modulated source (AM)
General Form (the PHASE parameter is only possible when XSPICE is enabled):
AM(VA VO MF FC TD PHASES)
Examples:
V1 12 0 AM(0.5 1 20K 5MEG 1m)
Name

Parameter

Default value

Units

VA

Amplitude



V, A

VO

Offset



V, A

MF

Modulating frequency



Hz

FC

Carrier frequency

$\frac{1}{TSTOP}$

Hz

TD

Signal delay



s

PHASES

Phase

0.0

degrees

The shape of the waveform is described by the following equation:
[\begin{array}{ll} {V\left( t \right) = V_{A}\left( {VO + \sin\left( {2\pi \cdot MF \cdot t} \right) + PHASES} \right)\sin\left( {2\pi \cdot FC \cdot t + PHASES} \right)} & \ \end{array}]
Transient noise source
General Form:
TRNOISE(NA NT NALPHA NAMP RTSAM RTSCAPT RTSEMT)
Examples:
VNoiw 1 0 DC 0 TRNOISE(20n 0.5n 0 0) $ white
VNoi1of 1 0 DC 0 TRNOISE(0 10p 1.1 12p) $ 1/f
VNoiw1of 1 0 DC 0 TRNOISE(20 10p 1.1 12p) $ white and 1/f
IALL 10 0 DC 0 trnoise(1m 1u 1.0 0.1m 15m 22u 50u)
$ white, 1/f, RTS
Transient noise is an experimental feature allowing (low frequency) transient noise injection and analysis. See Chapt. 15.3.10 for a detailed description. NA is the Gaussian noise rms voltage amplitude, NT is the time between sample values (breakpoints will be enforced on multiples of this value). NALPHA (exponent to the frequency dependency), NAMP (rms voltage or current amplitude) are the parameters for 1/f noise, RTSAM the random telegraph signal amplitude, RTSCAPT the mean of the exponential distribution of the trap capture time, and RTSEMT its emission time mean. White Gaussian, 1/f, and RTS noise may be combined into a single statement.
Name

Parameter

Default value

Units

NA

Rms noise amplitude (Gaussian)



V, A

NT

Time step



sec

NALPHA

1/f exponent

0 < α < 2



NAMP

Amplitude (1/f)



V, A

RTSAM

Amplitude



V, A

RTSCAPT

Trap capture time



sec

RTSEMT

Trap emission time



sec

If you set NT and RTSAM to 0, the noise option TRNOISE ... is ignored. Thus you may switch off the noise contribution of an individual voltage source VNOI by the command
alter @vnoi[trnoise] = [ 0 0 0 0 ] $ no noise
alter @vrts[trnoise] = [ 0 0 0 0 0 0 0] $ no noise
See Chapt. 17.5.3 for the alter command.
You may switch off all TRNOISE noise sources by setting
set notrnoise
to your .spiceinit file (for all your simulations) or into your control section in front of the next run or tran command (for this specific and all following simulations). The command
unset notrnoise
will reinstate all noise sources.
The noise generators are implemented into the independent voltage (vsrc) and current (isrc) sources.
Random voltage source
The TRRANDOM option yields statistically distributed voltage values, derived from the ngspice random number generator. These values may be used in the transient simulation directly within a circuit, e.g. for generating a specific noise voltage, but especially they may be used in the control of behavioral sources (B, E, G sources 5, voltage controllable A sources 12, capacitors 3.2.8, inductors 3.2.12, or resistors 3.2.4) to simulate the circuit dependence on statistically varying device parameters. A MonteCarlo simulation may thus be handled in a single simulation run.
General Form:
TRRANDOM(TYPE TS <TD <PARAM1 <PARAM2>>>)
Examples:
VR1 r1 0 dc 0 trrandom (2 10m 0 1) $ Gaussian
TYPE determines the random variates generated: 1 is uniformly distributed, 2 Gaussian, 3 exponential, 4 Poisson. TS is the duration of an individual voltage value. TD is a time delay with 0 V output before the random voltage values start up. PARAM1 and PARAM2 depend on the type selected.
TYPE

description

PARAM1

default

PARAM2

default


1

Uniform

Range

1

Offset

0


2

Gaussian

Standard Dev.

1

Mean

0


3

Exponential

Mean

1

Offset

0


4

Poisson

Lambda

1

Offset

0

External voltage or current input
General Form:
EXTERNAL
Examples:
Vex 1 0 dc 0 external
Iex i1 i2 dc 0 external <m = xx>
Voltages or currents may be set from the calling process, if ngspice is compiled as a shared library and loaded by the process. See Chapt. 19.6.3 for an explanation.
Arbitrary Phase Sources
The XSPICE option supports arbitrary phase independent sources that output at TIME=0.0 a value corresponding to some specified phase shift. Other versions of SPICE use the TD (delay time) parameter to set phaseshifted sources to their timezero value until the delay time has elapsed. The XSPICE phase parameter is specified in degrees and is included after the SPICE3 parameters normally used to specify an independent source. Partial XSPICE deck examples of usage for pulse and sine waveforms are shown below:
* Phase shift is specified after Berkeley defined parameters
* on the independent source cards. Phase shift for both of the
* following is specified as +45 degrees
*
v1 1 0 0.0 sin(0 1 1k 0 0 45.0)
r1 1 0 1k
*
v2 2 0 0.0 pulse(1 1 0 1e5 1e5 5e4 1e3 45.0)
r2 2 0 1k
*
Linear Dependent Sources
Ngspice allows circuits to contain linear dependent sources characterized by any of the four equations
i = gv

v = ev

i = fi

v = hi

where (g), (e), (f), and (h) are constants representing transconductance, voltage gain, current gain, and transresistance, respectively. Nonlinear dependent sources for voltages or currents (B, E, G) are described in Chapt. 5.
Gxxxx: Linear VoltageControlled Current Sources (VCCS)
General form:
GXXXXXXX N+ N NC+ NC VALUE <m=val>
Examples:
G1 2 0 5 0 0.1
n+ and n are the positive and negative nodes, respectively. Current flow is from the positive node, through the source, to the negative
node. nc+ and nc are the positive and negative controlling nodes, respectively. value is the transconductance (in mhos). m is an optional multiplier to the output current. val may be a numerical value or an expression according to 2.8.5 containing references to other parameters.
Exxxx: Linear VoltageControlled Voltage Sources (VCVS)
General form:
EXXXXXXX N+ N NC+ NC VALUE
Examples:
E1 2 3 14 1 2.0
n+ is the positive node, and n is the negative node. nc+ and nc are the positive and negative controlling nodes, respectively. value is the voltage gain.
Fxxxx: Linear CurrentControlled Current Sources (CCCS)
General form:
FXXXXXXX N+ N VNAM VALUE <m=val>
Examples:
F1 13 5 VSENS 5 m=2
n+ and n are the positive and negative nodes, respectively. Current flow is from the positive node, through the source, to the negative node. vnam is the name of a voltage source through which the controlling current flows. The direction of positive controlling current flow is from the positive node, through the source, to the negative node of vnam. value is the current gain. m is an optional multiplier to the output current.
Hxxxx: Linear CurrentControlled Voltage Sources (CCVS)
General form:
HXXXXXXX n+ n vnam value
Examples:
HX 5 17 VZ 0.5K
n+ and n are the positive and negative nodes, respectively. vnam is the name of a voltage source through which the controlling current flows. The direction of positive controlling current flow is from the positive node, through the source, to the negative node of vnam. value is the transresistance (in ohms).
Polynomial Source Compatibility
Dependent polynomial sources available in SPICE2G6 are fully supported in ngspice using the XSPICE extension (25.1). The form used to specify these sources is shown in Table 4.1. For details on its usage please see Chapt. 5.5.
Dependent Polynomial Sources
Source Type
Instance Card
POLYNOMIAL VCVS
EXXXXXXX N+ N POLY(ND) NC1+ NC1 P0 (P1...)
POLYNOMIAL VCCS
GXXXXXXX N+ N POLY(ND) NC1+ NC1 P0 (P1...)
POLYNOMIAL CCCS
FXXXXXXX N+ N POLY(ND) VNAM1 !VNAM2...? P0 (P1...)
POLYNOMIAL CCVS
HXXXXXXX N+ N POLY(ND) VNAM1 !VNAM2...? P0 (P1...)
Table 4.1: Dependent Polynomial Sources
Nonlinear Dependent Sources (Behavioral Sources)
The nonlinear dependent sources B ( see Chapt. 5.1), E (see 5.2), G see (5.3) described in this chapter allow to generate voltages or currents that result from evaluating a mathematical expression. Internally E and G sources are converted to the more general B source. All three sources may be used to introduce behavioral modeling and analysis.
Bxxxx: Nonlinear dependent source (ASRC)
Syntax and usage
General form:
BXXXXXXX n+ n <i=expr> <v=expr> <tc1=value> <tc2=value>
+ <temp=value> <dtemp=value>
Examples:
B1 0 1 I=cos(v(1))+sin(v(2))
B2 0 1 V=ln(cos(log(v(1,2)^2)))v(3)^4+v(2)^v(1)
B3 3 4 I=17
B4 3 4 V=exp(pi^i(vdd))
B5 2 0 V = V(1) < {Vlow} ? {Vlow} :
+ V(1) > {Vhigh} ? {Vhigh} : V(1)
n+ is the positive node, and n is the negative node. The values of the V and I parameters determine the voltages and currents across and through the device, respectively. If I is given then the device is a current source, and if V is given the device is a voltage source. One and only one of these parameters must be given.
A simple model is implemented for temperature behavior by the formula:
[\begin{array}{ll} {I\left( T \right) = I\left( {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right)\left( 1 + TC_{1}\left( {T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack}} \right) + TC_{2}\left( T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack})^{2} \right) \right.} & \ \end{array}]
or
[\begin{array}{ll} {V\left( T \right) = V\left( {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right)\left( 1 + TC_{1}\left( {T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack}} \right) + TC_{2}\left( T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack})^{2} \right) \right.} & \ \end{array}]
In the above formula, `(T)' represents the instance temperature, which can be explicitly set using the temp keyword or calculated using the circuit temperature and dtemp, if present. If both temp and dtemp are specified, the latter is ignored.
The smallsignal AC behavior of the nonlinear source is a linear dependent source (or sources) with a proportionality constant equal to the derivative (or derivatives) of the source at the DC operating point. The expressions given for V and I may be any function of voltages and currents through voltage sources in the system.
The following functions of a single real variable are defined:
 Trigonometric functions:
cos, sin, tan, acos, asin, atan  Hyperbolic functions:
cosh, sinh, acosh, asinh, atanh  Exponential and logarithmic:
exp, ln, log, log10 (ln, log with base e, log10 with base 10)  Other:
abs, sqrt, u, u2, uramp, floor, ceil, i  Functions
of two variables are: min, max, pow, **, pwr, ^  Functions
of three variables are: a ? b:c
The function `u' is the unit step function, with a value of one for arguments greater than zero and a value of zero for arguments less than zero. The function `u2' returns a value of zero for arguments less than zero, one for arguments greater than one and assumes the value of the argument between these limits. The function `uramp' is the integral of the unit step: for an input x, the value is zero if x is less than zero, or if x is greater than zero the value is x. These three functions are useful in synthesizing piecewise nonlinear functions, though convergence may be adversely affected.
The function i(xyz) returns the current through the first node of device instance xyz.
The following standard operators are defined: +, , *, /, ^, unary 
Logical operators are !=, <>, >=, <=, ==, >, <, , &&, ! .
A ternary function is defined as a ? b : c , which means IF a, THEN b, ELSE c. Be sure to place a space in front of `?' to allow the parser distinguishing it from other tokens.
The B source functions pow, **, ^, and pwr need some special care. Avoiding undefined regions in x1, they differ from the common mathematical usage (and from the functions depicted in chapt. 2.8.5).
The functions y = pow(x1,x2), x1**x2, and x1^x2 , all of them describing (y = x1^{x2}), resolve to the following:
y = pow(fabs(x1), x2)
pow in the preceding line is the standard C math library function.
The function y = pwr(x1,x2) resolves to
if (x1 < 0.0)
y = (pow(x1, x2));
else
y = (pow(x1, x2));
pow here again is the standard C math library function.
Example: Ternary function
* B source test Clamped voltage source
* C. P. Basso "Switchedmode power supplies", New York, 2008
.param Vhigh = 4.6
.param Vlow = 0.4
Vin1 1 0 DC 0 PWL(0 0 1u 5)
Bcl 2 0 V = V(1) < Vlow ? Vlow : V(1) > Vhigh ? Vhigh : V(1)
.control
unset askquit
tran 5n 1u
plot V(2) vs V(1)
.endc
.end
If the argument of log, ln, or sqrt becomes less than zero, the absolute value of the argument is used. If a divisor becomes zero or the argument of log or ln becomes zero, an error will result. Other problems may occur when the argument for a function in a partial derivative enters a region where that function is undefined.
Parameters may be used like {Vlow} shown in the example above. Parameters will be evaluated upon set up of the circuit, vectors like V(1) will be evaluated during the simulation.
To get time into the expression you can integrate the current from a constant current source with a capacitor and use the resulting voltage (don't forget to set the initial voltage across the capacitor).
Nonlinear resistors, capacitors, and inductors may be synthesized with the nonlinear dependent source. Nonlinear resistors, capacitors and inductors are implemented with their linear counterparts by a change of variables implemented with the nonlinear dependent source. The following subcircuit will implement a nonlinear capacitor:
Example: Non linear capacitor
.Subckt nlcap pos neg
* Bx: calculate f(input voltage)
Bx 1 0 v = f(v(pos,neg))
* Cx: linear capacitance
Cx 2 0 1
* Vx: Ammeter to measure current into the capacitor
Vx 2 1 DC 0Volts
* Drive the current through Cx back into the circuit
Fx pos neg Vx 1
.ends
Example for f(v(pos,neg)):
Bx 1 0 V = v(pos,neg)*v(pos,neg)
Nonlinear resistors or inductors may be described in a similar manner. An example for a nonlinear resistor using this template is shown below.
Example: Non linear resistor
* use of 'hertz' variable in nonlinear resistor
*.param rbase=1k
* some tests
B1 1 0 V = hertz*v(33)
B2 2 0 V = v(33)*hertz
b3 3 0 V = 6.283e3/(hertz+6.283e3)*v(33)
V1 33 0 DC 0 AC 1
*** Translate R1 10 0 R='1k/sqrt(HERTZ)' to B source ***
.Subckt nlres pos neg rb=rbase
* Bx: calculate f(input voltage)
Bx 1 0 v = 1 / {rb} / sqrt(HERTZ) * v(pos, neg)
* Rx: linear resistance
Rx 2 0 1
Example: Non linear resistor (continued)
* Vx: Ammeter to measure current into the resistor
Vx 2 1 DC 0Volts
* Drive the current through Rx back into the circuit
Fx pos neg Vx 1
.ends
Xres 33 10 nlres rb=1k
*Rres 33 10 1k
Vres 10 0 DC 0
.control
define check(a,b) vecmax(abs(a  b))
ac lin 10 100 1k
* some checks
print v(1) v(2) v(3)
if check(v(1), frequency) < 1e12
echo "INFO: ok"
end
plot vres#branch
.endc
.end
Special BSource Variables time, temper, hertz
The special variables time and temper are available in a transient analysis, reflecting the actual simulation time and circuit temperature. temper returns the circuit temperature, given in degree C (see 2.11). The variable hertz is available in an AC analysis. time is zero in the AC analysis, hertz is zero during transient analysis. Using the variable hertz may cost some CPU time if you have a large circuit, because for each frequency the operating point has to be determined before calculating the AC response.
par('expression')
The B source syntax may also be used in output lines like .plot as algebraic expressions for output (see Chapt.15.6.6 ).
Piecewise Linear Function: pwl
Both B source types may contain a piecewise linear dependency of one network variable:
Example: pwl_current
Bdio 1 0 I = pwl(v(A), 0,0, 33,10m, 100,33m, 200,50m)
v(A) is the independent variable x. Each pair of values following describes the x,y functional relation: In this example at node A voltage of 0V the current of 0A is generated  next pair gives 10mA flowing from ground to node 1 at 33V on node A and so forth.
The same is possible for voltage sources:
Example: pwl_voltage
Blimit b 0 V = pwl(v(1), 4,0, 2,2, 2,4, 4,5, 6,5)
Monotony of the independent variable in the pwl definition is checked  nonmonotonic x entries will stop the program execution. v(1) may be replaced by a controlling current source. v(1) may also be replaced by an expression, e.g. ( 2 i\left( V_{in} \right)). The value pairs may also be parameters, and have to be predefined by a .param statement. An example for the pwl function using all of these options is shown below.
Example: pwl function in B source
Demonstrates usage of the pwl function in an B source (ASRC)
* Also emulates the TABLE function with limits
.param x0=4 y0=0
.param x1=2 y1=2
.param x2=2 y2=2
.param x3=4 y3=1
.param xx0=x01
.param xx3=x3+1
Vin 1 0 DC=0V
R 1 0 2
* no limits outside of the tabulated x values
* (continues linearily)
Btest2 2 0 I = pwl(v(1),'x0','y0','x1','y1','x2','y2','x3','y3')
* like TABLE function with limits:
Btest3 3 0 I = (v(1) < 'x0') ? 'y0' : (v(1) < 'x3') ?
+ pwl(v(1),'x0','y0','x1','y1','x2','y2','x3','y3') : 'y3'
* more efficient and elegant TABLE function with limits
*(voltage controlled):
Btest4 4 0 I = pwl(v(1),
+ 'xx0','y0', 'x0','y0',
+ 'x1','y1',
+ 'x2','y2',
+ 'x3','y3', 'xx3','y3')
*
* more efficient and elegant TABLE function with limits
* (controlled by current):
Btest5 5 0 I = pwl(2*i(Vin),
+ 'xx0','y0', 'x0','y0',
+ 'x1','y1',
+ 'x2','y2',
+ 'x3','y3', 'xx3','y3')
Rint2 2 0 1
Rint3 3 0 1
Rint4 4 0 1
Rint5 5 0 1
.control
dc Vin 6 6 0.2
plot v(2) v(3) v(4)0.5 v(5)+0.5
.endc
.end
Exxxx: nonlinear voltage source
VOL
General form:
EXXXXXXX n+ n vol='expr'
Examples:
E41 4 0 vol = 'V(3)*V(3)Offs'
Expression may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in Chapt. 5.1. It may contain parameters (2.8.1) and the special variables time, temper, hertz (5.1.2). ' or { } may be used to delimit the function.
VALUE
Optional syntax:
EXXXXXXX n+ n value={expr}
Examples:
E41 4 0 value = {V(3)*V(3)Offs}
The '=' sign is optional.
TABLE
Data may be entered from the listings of a data table similar to the pwl BSource (5.1.4). Data are grouped into x, y pairs. Expression may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in Chapt. 5.1. It may contain parameters (2.8.1). ' or { } may be used to delimit the function. Expression delivers the xvalue, which is used to generate a corresponding yvalue according to the tabulated value pairs, using linear interpolation. If the xvalue is below x0 , y0 is returned, above x2 y2 is returned (limiting function). The value pairs have to be real numbers, parameters are not allowed.
Syntax for data entry from table:
Exxx n1 n2 TABLE {expression} = (x0, y0) (x1, y1) (x2, y2)
Example (simple comparator):
ECMP 11 0 TABLE {V(10,9)} = (5mV, 0V) (5mV, 5V)
An '=' sign may follow the keyword TABLE.
POLY
see ESource at Chapt. 5.5.
LAPLACE
Currently ngspice does not offer a direct ESource element with the LAPLACE option. There is however a XSPICE code model equivalent called s_xfer (see Chapt. 12.2.16), which you may invoke manually. The XSPICE option has to be enabled (32.1). AC (15.3.1) and transient analysis (15.3.9) is supported.
The following ESource:
ELOPASS 4 0 LAPLACE {V(1)}
+ {5 * (s/100 + 1) / (s^2/42000 + s/60 + 1)}
may be replaced by:
AELOPASS 1 int_4 filter1
.model filter1 s_xfer(gain=5
+ num_coeff=[{1/100} 1]
+ den_coeff=[{1/42000} {1/60} 1]
+ int_ic=[0 0])
ELOPASS 4 0 int_4 0 1
where you have the voltage of node 1 as input, an intermediate output node int_4 and an Esource as buffer to keep the name `ELOPASS' available if further processing is required.
If the controlling expression is more complex than just a voltage node, you may add a BSource (5.1) for evaluating the expression before entering the Adevice.
ESource with complex controlling expression:
ELOPASS 4 0 LAPLACE {V(1)*v(2)} {10 / (s/6800 + 1)}
may be replaced by:
BELOPASS int_1 0 V=V(1)*v(2)
AELOPASS int_1 int_4 filter1
.model filter1 s_xfer(gain=10
+ num_coeff=[1]
+ den_coeff=[{1/6800} 1]
+ int_ic=[0])
ELOPASS 4 0 int_4 0 1
Gxxxx: nonlinear current source
CUR
General form:
GXXXXXXX n+ n cur='expr' <m=val>
Examples:
G51 55 225 cur = 'V(3)*V(3)Offs'
Expression may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in Chapt. 5.1. It may contain parameters (2.8.1) and special variables (5.1.2). m is an optional multiplier to the output current. val may be a numerical value or an expression according to 2.8.5 containing only references to other parameters (no node voltages or branch currents!), because it is evaluated before the simulation commences.
VALUE
Optional syntax:
GXXXXXXX n+ n value='expr' <m=val>
Examples:
G51 55 225 value = 'V(3)*V(3)Offs'
The '=' sign is optional.
TABLE
A data entry by a tabulated listing is available with syntax similar to the ESource (see Chapt. 5.2.3).
Syntax for data entry from table:
Gxxx n1 n2 TABLE {expression} =
+ (x0, y0) (x1, y1) (x2, y2) <m=val>
Example (simple comparator with current output and voltage control):
GCMP 0 11 TABLE {V(10,9)} = (5MV, 0V) (5MV, 5V)
R 11 0 1k
m is an optional multiplier to the output current. val may be a numerical value or an expression according to 2.8.5 containing only references to other parameters (no node voltages or branch currents!), because it is evaluated before the simulation commences. An '=' sign may follow the keyword TABLE.
POLY
see ESource at Chapt. 5.5.
LAPLACE
See ESource, Chapt. 5.2.5 , for an equivalent code model replacement.
Example
An example file is given below.
Example input file:
VCCS, VCVS, nonlinear dependency
.param Vi=1
.param Offs='0.01*Vi'
* VCCS depending on V(3)
B21 int1 0 V = V(3)*V(3)
G1 21 22 int1 0 1
* measure current through VCCS
vm 22 0 dc 0
R21 21 0 1
* new VCCS depending on V(3)
G51 55 225 cur = 'V(3)*V(3)Offs'
* measure current through VCCS
vm5 225 0 dc 0
R51 55 0 1
* VCVS depending on V(3)
B31 int2 0 V = V(3)*V(3)
E1 1 0 int2 0 1
R1 1 0 1
* new VCVS depending on V(3)
E41 4 0 vol = 'V(3)*V(3)Offs'
R4 4 0 1
* control voltage
V1 3 0 PWL(0 0 100u {Vi})
.control
unset askquit
tran 10n 100u uic
plot i(E1) i(E41)
plot i(vm) i(vm5)
.endc
.end
Debugging a behavioral source
The B, E, G, sources and the behavioral R, C, L elements are powerful tools to set up user defined models. Unfortunately debugging these models is not very comfortable.
Example input file with bug (log(2)):
B source debugging
V1 1 0 1
V2 2 0 2
E41 4 0 vol = 'V(1)*log(V(2))'
.control
tran 1 1
.endc
.end
The input file given above results in an error message:
Error: 2 out of range for log
In this trivial example, the reason and location for the bug is obvious. However, if you have several equations using behavioral sources, and several occurrences of the log function, then debugging is nearly impossible.
However, if the variable ngdebug (see 17.7) is set (e.g. in file .spiceinit), a more distinctive error message is issued that (after some closer investigation) will reveal the location and value of the buggy parameter.
Detailed error message for input file with bug (log(2)):
Error: 2 out of range for log
calling PTeval, tree =
(v0) * (log (v1))
d / d v0 : log (v1)
d / d v1 : (v0) * ((0.434294) / (v1))
values: var0 = 1
var1 = 2
If variable strict_errorhandling (see 17.7) is set, ngspice exits after this message. If not, gmin and source stepping may be started, typically without success.
POLY Sources
Polynomial sources are only available when the XSPICE option (see 32) is enabled.
E voltage source, G current source
General form:
EXXXX N+ N POLY(ND) NC1+ NC1 (NC2+ NC2...) P0 (P1...)
Example:
ENONLIN 100 101 POLY(2) 3 0 4 0 0.0 13.6 0.2 0.005
POLY(ND) Specifies the number of dimensions of the polynomial. The number of pairs of controlling nodes must be equal to the number of dimensions.
(N+) and (N) nodes are output nodes. Positive current flows from the (+) node through the source to the () node.
The <NC1+> and <NC1> are in pairs and define a set of controlling voltages. A particular node can appear more than once, and the output and controlling nodes need not be different.
The example yields a voltage output controlled by two input voltages v(3,0) and v(4,0). Four polynomial coefficients are given. The equivalent function to generate the output is:
0 + 13.6 * v(3) + 0.2 * v(4) + 0.005 * v(3) * v(3)
Generally you will set the equation according to
POLY(1) y = p0 + p1*X1 + p2*X1*X1 + p3*X1*X1*X1 + ...
POLY(2) y = p0 + p1*X1 + p2*X2 +
+ p3*X1*X1 + p4*X2*X1 + p5*X2*X2 +
+ p6*X1*X1*X1 + p7*X2*X1*X1 + p8*X2*X2*X1 +
+ p9*X2*X2*X2 + ...
POLY(3) y = p0 + p1*X1 + p2*X2 + p3*X3 +
+ p4*X1*X1 + p5*X2*X1 + p6*X3*X1 +
+ p7*X2*X2 + p8*X2*X3 + p9*X3*X3 + ...
where X1 is the voltage difference of the first input node pair, X2 of the second pair and so on. Keeping track of all polynomial coefficient is rather tedious for large polynomials.
F voltage source, H current source
General form:
FXXXX N+ N POLY(ND) V1 (V2 V3 ...) P0 (P1...)
Example:
FNONLIN 100 101 POLY(2) VDD Vxx 0 0.0 13.6 0.2 0.005
POLY(ND) Specifies the number of dimensions of the polynomial. The number of controlling sources must be equal to the number of dimensions.
(N+) and (N) nodes are output nodes. Positive current flows from the (+) node through the source to the () node.
V1 (V2 V3 ...) are the controlling voltage sources. Control variable is the current through these sources.
P0 (P1...) are the coefficients, as have been described in 5.5.1.
Transmission Lines
Ngspice implements both the original SPICE3f5 transmission lines models and the one introduced with KSPICE. The latter provide an improved transient analysis of lossy transmission lines. Unlike SPICE models that use the statebased approach to simulate lossy transmission lines, KSPICE simulates lossy transmission lines and coupled multiconductor line systems using the recursive convolution method. The impulse response of an arbitrary transfer function can be determined by deriving a recursive convolution from the Pade approximations of the function. We use this approach for simulating each transmission line's characteristics and each multiconductor line's modal functions. This method of lossy transmission line simulation has been proved to give a speedup of one to two orders of magnitude over SPICE3f5.
Lossless Transmission Lines
General form:
TXXXXXXX N1 N2 N3 N4 Z0=VALUE <TD=VALUE>
+ <F=FREQ <NL=NRMLEN>> <IC=V1, I1, V2, I2>
Examples:
T1 1 0 2 0 Z0=50 TD=10NS
n1 and n2 are the nodes at port 1; n3 and n4 are the nodes at port 2. z0 is the characteristic impedance. The length of the line may be expressed in either of two forms. The transmission delay, td, may be specified directly (as td=10ns, for example). Alternatively, a frequency f may be given, together with nl, the normalized electrical length of the transmission line with respect to the wavelength in the line at the frequency `f'. If a frequency is specified but nl is omitted, 0.25 is assumed (that is, the frequency is assumed to be the quarterwave frequency). Note that although both forms for expressing the line length are indicated as optional, one of the two must be specified.
Note that this element models only one propagating mode. If all four nodes are distinct in the actual circuit, then two modes may be excited. To simulate such a situation, two transmissionline elements are required. (see the example in Chapt. 21.7 for further clarification.) The (optional) initial condition specification consists of the voltage and current at each of the transmission line ports. Note that the initial conditions (if any) apply only if the UIC option is specified on the .TRAN control line.
Note that a lossy transmission line (see below) with zero loss may be more accurate than the lossless transmission line due to implementation details.
Lossy Transmission Lines
General form:
OXXXXXXX n1 n2 n3 n4 mname
Examples:
O23 1 0 2 0 LOSSYMOD
OCONNECT 10 5 20 5 INTERCONNECT
This is a twoport convolution model for single conductor lossy transmission lines. n1 and n2 are the nodes at port 1; n3 and n4 are the nodes at port 2. Note that a lossy transmission line with zero loss may be more accurate than the lossless transmission line due to implementation details.
Lossy Transmission Line Model (LTRA)
The uniform RLC/RC/LC/RG transmission line model (referred to as the LTRA model henceforth) models a uniform constantparameter distributed transmission line. The RC and LC cases may also be modeled using the URC and TRA models; however, the newer LTRA model is usually faster and more accurate than the others. The operation of the LTRA model is based on the convolution of the transmission line's impulse responses with its inputs (see [8]). The LTRA model takes a number of parameters, some of which must be given and some of which are optional.
Name

Parameter

Units/Type

Default

Example

R

resistance/length

$\frac{\Omega}{unit}$

0.0

0.2

L

inductance/length

$\frac{H}{unit}$

0.0

9.13e9

G

conductance/length

$\frac{mhos}{unit}$

0.0

0.0

C

capacitance/length

$\frac{F}{unit}$

0.0

3.65e12

LEN

length of line

unit

no default

1.0

REL

breakpoint control

arbitrary unit

1

0.5

ABS

breakpoint control

1

5


NOSTEPLIMIT

don't limit timestep to less than line delay

flag

not set

set

NO CONTROL

don't do complex timestep control

flag

not set

set

LININTERP

use linear interpolation

flag

not set

set

MIXEDINTERP

use linear when quadratic seems bad

flag

not set

set

COMPACTREL

special reltol for history compaction

RELTOL

1.0e3


COMPACTABS

special abstol for history compaction

ABSTOL

1.0e9


TRUNCNR

use NewtonRaphson method for timestep control

flag

not set

set

TRUNCDONTCUT

don't limit timestep to keep impulseresponse errors low

flag

not set

set

The following types of lines have been implemented so far:
 RLC (uniform transmission line with series loss only),
 RC (uniform RC line),
 LC (lossless transmission line),
 RG (distributed series resistance and parallel conductance only).
Any other combination will yield erroneous results and should not be tried. The length LEN of the line must be specified. NOSTEPLIMIT is a flag that will remove the default restriction of limiting timesteps to less than the line delay in the RLC case. NO CONTROL is a flag that prevents the default limiting of the timestep based on convolution error criteria in the RLC and RC cases. This speeds up simulation but may in some cases reduce the accuracy of results. LININTERP is a flag that, when specified, will use linear interpolation instead of the default quadratic interpolation for calculating delayed signals. MIXEDINTERP is a flag that, when specified, uses a metric for judging whether quadratic interpolation is not applicable and if so uses linear interpolation; otherwise it uses the default quadratic interpolation. TRUNCDONTCUT is a flag that removes the default cutting of the timestep to limit errors in the actual calculation of impulseresponse related quantities. COMPACTREL and COMPACTABS are quantities that control the compaction of the past history of values stored for convolution. Larger values of these lower accuracy but usually increase simulation speed. These are to be used with the TRYTOCOMPACT option, described in the .OPTIONS section. TRUNCNR is a flag that turns on the use of NewtonRaphson iterations to determine an appropriate timestep in the timestep control routines. The default is a trial and error procedure by cutting the previous timestep in half. REL and ABS are quantities that control the setting of breakpoints.
The option most worth experimenting with for increasing the speed of simulation is REL. The default value of 1 is usually safe from the point of view of accuracy but occasionally increases computation time. A value greater than 2 eliminates all breakpoints and may be worth trying depending on the nature of the rest of the circuit, keeping in mind that it might not be safe from the viewpoint of accuracy.
Breakpoints may usually be entirely eliminated if it is expected the circuit will not display sharp discontinuities. Values between 0 and 1 are usually not required but may be used for setting many breakpoints.
COMPACTREL may also be experimented with when the option TRYTOCOMPACT is specified in a .OPTIONS card. The legal range is between 0 and 1. Larger values usually decrease the accuracy of the simulation but in some cases improve speed. If TRYTOCOMPACT is not specified on a .OPTIONS card, history compaction is not attempted and accuracy is high.
NO CONTROL, TRUNCDONTCUT and NOSTEPLIMIT also tend to increase speed at the expense of accuracy.
Uniform Distributed RC Lines
General form:
UXXXXXXX n1 n2 n3 mname l=len <n=lumps>
Examples:
U1 1 2 0 URCMOD L=50U
URC2 1 12 2 UMODL l=1MIL N=6
n1 and n2 are the two element nodes the RC line connects, while n3 is the node the capacitances are connected to. mname is the model name, len is the length of the RC line in meters. lumps, if specified, is the number of lumped segments to use in modeling the RC line (see the model description for the action taken if this parameter is omitted).
Uniform Distributed RC Model (URC)
The URC model is derived from a model proposed by L. Gertzberg in 1974. The model is accomplished by a subcircuit type expansion of the URC line into a network of lumped RC segments with internally generated nodes. The RC segments are in a geometric progression, increasing toward the middle of the URC line, with (K) as a proportionality constant. The number of lumped segments used, if not specified for the URC line device, is determined by the following formula:
[\begin{array}{ll} {N = \frac{\log\left {F_{\lbrack font\ rm\ \lbrack char\ m\ mathalpha\rbrack\lbrack char\ a\ mathalpha\rbrack\lbrack char\ x\ mathalpha\rbrack\rbrack}\frac{R}{L}\frac{C}{L}2\pi L^{2}\left \frac{\left( {K  1} \right)}{K} \right^{2}} \right}{\log K}} & \ \end{array}]The URC line is made up strictly of resistor and capacitor segments unless the ISPERL parameter is given a nonzero value, in which case the capacitors are replaced with reverse biased diodes with a zerobias junction capacitance equivalent to the capacitance replaced, and with a saturation current of ISPERL amps per meter of transmission line and an optional series resistance equivalent to RSPERL ohms per meter.
Name

Parameter

Units

Default

Example

Area

K

Propagation Constant



2.0

1.2



FMAX

Maximum Frequency of interest

Hz

1.0 G

6.5 Meg



RPERL

Resistance per unit length

$\frac{\Omega}{m}$

1000

10



CPERL

Capacitance per unit length

$\frac{F}{m}$

10e15

1 p



ISPERL

Saturation Current per unit length

$\frac{A}{m}$

0





RSPERL

Diode Resistance per unit length

$\frac{\Omega}{m}$

0





KSPICE Lossy Transmission Lines
Unlike SPICE3, which uses the statebased approach to simulate lossy transmission lines, KSPICE simulates lossy transmission lines and coupled multiconductor line systems using the recursive convolution method. The impulse response of an arbitrary transfer function can be determined by deriving a recursive convolution from the Pade approximations of the function. NGSPICE is using this approach for simulating each transmission line's characteristics and each multiconductor line's modal functions. This method of lossy transmission line simulation has shown to give a speedup of one to two orders of magnitude over SPICE3E. Please note that the following two models will support only transient simulation, no ac.
Additional Documentation Available:
 S. Lin and E. S. Kuh, `Pade Approximation Applied to Transient Simulation of Lossy Coupled Transmission Lines,' Proc. IEEE MultiChip Module Conference, 1992, pp. 5255.
 S. Lin, M. MarekSadowska, and E. S. Kuh, `SWEC: A StepWise Equivalent Conductance Timing Simulator for CMOS VLSI Circuits,' European Design Automation Conf., February 1991, pp. 142148.
 S. Lin and E. S. Kuh, `Transient Simulation of Lossy Interconnect,' Proc. Design Automation Conference, Anaheim, CA, June 1992, pp. 8186.
Single Lossy Transmission Line (TXL)
General form:
YXXXXXXX N1 0 N2 0 mname <LEN=LENGTH>
Example:
Y1 1 0 2 0 ymod LEN=2
.MODEL ymod txl R=12.45 L=8.972e9 G=0 C=0.468e12 length=16
n1 and n2 are the nodes of the two ports. The optional instance parameter len is the length of the line and may be expressed in multiples of [(unit)]. Typically (unit) is given in meters. len will override the model parameter **length **for the specific instance only.
The TXL model takes a number of parameters:
Name

Parameter

Units/Type

Default

Example

R

resistance/length

$\frac{\Omega}{unit}$

0.0

0.2

L

inductance/length

$\frac{H}{unit}$

0.0

9.13e9

G

conductance/length

$\frac{mhos}{unit}$

0.0

0.0

C

capacitance/length

$\frac{F}{unit}$

0.0

3.65e12

LENGTH

length of line

unit

no default

1.0

Model parameter length must be specified as a multiple of (unit). Typically (unit) is given in [m]. For transient simulation only.
Coupled Multiconductor Line (CPL)
The CPL multiconductor line model is in theory similar to the RLGC model, but without frequency dependent loss (neither skin effect nor frequencydependent dielectric loss). Up to 8 coupled lines are supported in NGSPICE.
General form:
PXXXXXXX NI1 NI2...NIX GND1 NO1 NO2...NOX GND2 mname <LEN=LENGTH>
Example:
P1 in1 in2 0 b1 b2 0 PLINE
.model PLINE CPL length={Len}
+R=1 0 1
+L={L11} {L12} {L22}
+G=0 0 0
+C={C11} {C12} {C22}
.param Len=1 Rs=0
+ C11=9.143579E11 C12=9.78265E12 C22=9.143578E11
+ L11=3.83572E7 L12=8.26253E8 L22=3.83572E7
ni1 ... nix are the nodes at port 1 with gnd1; no1 ... nox are the nodes at port 2 with gnd2. The optional instance parameter len is the length of the line and may be expressed in multiples of [(unit)]. Typically (unit) is given in meters. len will override the model parameter **length **for the specific instance only.
The CPL model takes a number of parameters:
Name

Parameter

Units/Type

Default

Example

R

resistance/length

$\frac{\Omega}{unit}$

0.0

0.2

L

inductance/length

$\frac{H}{unit}$

0.0

9.13e9

G

conductance/length

$\frac{mhos}{unit}$

0.0

0.0

C

capacitance/length

$\frac{F}{unit}$

0.0

3.65e12

LENGTH

length of line

unit

no default

1.0

All RLGC parameters are given in Maxwell matrix form. For the R and G matrices the diagonal elements must be specified, for L and C matrices the lower or upper triangular elements must specified. The parameter LENGTH is a scalar and is mandatory. For transient simulation only.
Diodes
Junction Diodes
General form:
DXXXXXXX n+ n mname <area=val> <m=val> <pj=val> <off>
+ <ic=vd> <temp=val> <dtemp=val>
Examples:
DBRIDGE 2 10 DIODE1
DCLMP 3 7 DMOD AREA=3.0 IC=0.2
The pn junction (diode) implemented in ngspice expands the one found in SPICE3f5. Perimeter effects and high injection level have been introduced into the original model and temperature dependence of some parameters has been added. n+ and n are the positive and negative nodes, respectively. mname is the model name. Instance parameters may follow, dedicated to only the diode described on the respective line.** area** is the area scale factor, which may scale the saturation current given by the model parameters (and others, see table below). pj is the perimeter scale factor, scaling the sidewall saturation current and its associated capacitance. m is a multiplier of area and perimeter, and** off** indicates an (optional) starting condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification using ic is intended for use with the uic option on the .tran control line, when a transient analysis is desired starting from other than the quiescent operating point. You should supply the initial voltage across the diode there. The (optional) temp value is the temperature at which this device is to operate, and overrides the temperature specification on the .option control line. The temperature of each instance can be specified as an offset to the circuit temperature with the dtemp option.
Diode Model (D)
The dc characteristics of the diode are determined by the parameters is and n. An ohmic resistance, rs, is included. Charge storage effects are modeled by a transit time, tt, and a nonlinear depletion layer capacitance that is determined by the parameters cjo, vj, and m. The temperature dependence of the saturation current is defined by the parameters eg, the energy, and xti, the saturation current temperature exponent. The nominal temperature where these parameters were measured is tnom, which defaults to the circuitwide value specified on the .options control line. Reverse breakdown is modeled by an exponential increase in the reverse diode current and is determined by the parameters bv and ibv (both of which are positive numbers).
Junction DC parameters
Name

Parameter

Units

Default

Example

Scale factor

IS (JS)

Saturation current

A

1.0e14

1.0e16

area

JSW

Sidewall saturation current

A

0.0

1.0e15

perimeter

N

Emission coefficient



1

1.5


RS

Ohmic resistance

Ω

0.0

100

$\frac{1}{area}$

BV

Reverse breakdown voltage

V

∞

40


IBV

Current at breakdown voltage

A

1.0e3

1.0e4


NBV

Breakdown Emission Coefficient



N

1.2


IKF (IK)

Forward knee current

A

0.0

1.0e3


IKR

Reverse knee current

A

0.0

1.0e3


JTUN

Tunneling saturation current

A

0.0

area


JTUNSW

Tunneling sidewall saturation current

A

0.0

perimeter


NTUN

Tunneling emission coefficient



30


XTITUN

Tunneling saturation current exponential



3


KEG

EG correction factor for tunneling



1.0


ISR

Recombination saturation current

A

1e14

1pA

area

NR

Recombination current emission coefficient



1

2

Junction capacitance parameters
Name

Parameter

Units

Default

Example

Scale factor

CJO (CJ0)

Zerobias junction bottomwall capacitance

F

0.0

2pF

area

CJP (CJSW)

Zerobias junction sidewall capacitance

F

0.0

.1pF

perimeter

FC

Coefficient for forwardbias depletion bottomwall capacitance formula



0.5




FCS

Coefficient for forwardbias depletion sidewall capacitance formula



0.5




M (MJ)

Area junction grading coefficient



0.5

0.5


MJSW

Periphery junction grading coefficient



0.33

0.5


VJ (PB)

Junction potential

V

1

0.6


PHP

Periphery junction potential

V

1

0.6


TT

Transittime

sec

0

0.1ns

Temperature effects
Name

Parameter

Units

Default

Example

EG

Activation energy

eV

1.11

$\begin{array}{ll}
1.11 & {Si} \\
0.69 & {Sbd} \\
0.67 & {Ge} \\
\end{array}$

TM1

1st order tempco for MJ

$\frac{1}{C}$

0.0



TM2

2nd order tempco for MJ

$\frac{1}{C^{2}}$

0.0



TNOM (TREF)

Parameter measurement temperature

C

27

50

TRS1 (TRS)

1st order tempco for RS

$\frac{1}{C}$

0.0



TRS2

2nd order tempco for RS

$\frac{1}{C^{2}}$

0.0



TM1

1st order tempco for MJ

$\frac{1}{C}$

0.0



TM2

2nd order tempco for MJ

$\frac{1}{C^{2}}$

0.0



TTT1

1st order tempco for TT

$\frac{1}{C}$

0.0



TTT2

2nd order tempco for TT

$\frac{1}{C^{2}}$

0.0



XTI

Saturation current temperature exponent



3.0

$\begin{array}{ll}
3.0 & {pn} \\
2.0 & {Sbd} \\
\end{array}$

TLEV

Diode temperature equation selector



0


TLEVC

Diode capac. temperature equation selector



0


CTA (CTC)

Area junct. cap. temperature coefficient

$\frac{1}{C}$

0.0



CTP

Perimeter junct. cap. temperature coefficient

$\frac{1}{C}$

0.0



TCV

Breakdown voltage temperature coefficient

$\frac{1}{C}$

0.0



Noise modeling
Name

Parameter

Units

Default

Example

Scale factor

KF

Flicker noise coefficient



0


AF

Flicker noise exponent



1

Diode models may be described in the input file (or an file included by .inc) according to the following example:
General form:
.model mname type(pname1=pval1 pname2=pval2 ... )
Examples:
.model DMOD D (bv=50 is=1e13 n=1.05)
Diode Equations
The junction diode is the basic semiconductor device and the simplest one in ngspice, but its model is quite complex, even when not all the physical phenomena affecting a pn junction are handled. The diode is modeled in three different regions:
 Forward bias: the anode is more positive than the cathode, the diode is `on' and can conduct large currents. To avoid convergence problems and unrealistic high current, it is prudent to specify a series resistance to limit current with the rs model parameter.
 Reverse bias: the cathode is more positive than the anode and the diode is `off'. A reverse bias diode conducts a small leakage current.
 Breakdown: the breakdown region is modeled only if the bv model parameter is given. When a diode enters breakdown the current increases exponentially (remember to limit it); bv is a positive value.
Parameters Scaling
Model parameters are scaled using the unitless parameters area and pj and the multiplier m as depicted below:
(AREA_{eff} = {\lbrack font\ rm\ \lbrack char\ A\ mathalpha\rbrack\lbrack char\ R\ mathalpha\rbrack\lbrack char\ E\ mathalpha\rbrack\lbrack char\ A\ mathalpha\rbrack\rbrack} m)
(PJ_{eff} = {\lbrack font\ rm\ \lbrack char\ P\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack} m)
(IS_{eff} = {\lbrack font\ rm\ \lbrack char\ I\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\rbrack} AREA_{eff} + {\lbrack font\ rm\ \lbrack char\ J\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\lbrack char\ W\ mathalpha\rbrack\rbrack} PJ_{eff})
(IBV_{eff} = {\lbrack font\ rm\ \lbrack char\ I\ mathalpha\rbrack\lbrack char\ B\ mathalpha\rbrack\lbrack char\ V\ mathalpha\rbrack\rbrack} AREA_{eff})
(IK_{eff} = {\lbrack font\ rm\ \lbrack char\ I\ mathalpha\rbrack\lbrack char\ K\ mathalpha\rbrack\rbrack} AREA_{eff})
(IKR_{eff} = {\lbrack font\ rm\ \lbrack char\ I\ mathalpha\rbrack\lbrack char\ K\ mathalpha\rbrack\lbrack char\ R\ mathalpha\rbrack\rbrack} AREA_{eff})
(CJ_{eff} = {\lbrack font\ rm\ \lbrack char\ C\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\lbrack char\ 0\ mathalpha\rbrack\rbrack} AREA_{eff})
(CJP_{eff} = {\lbrack font\ rm\ \lbrack char\ C\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\lbrack char\ P\ mathalpha\rbrack\rbrack} PJ_{eff})
Diode DC, Transient and AC model equations
The diode model has certain dc currents for bottom and sidewall components. Exemplary here is the equation for the bottom part:
[\begin{array}{ll} {I_{D} = \begin{cases} {IS_{eff}\left( {e^{\frac{qV_{D}}{NkT}}  1} \right) + V_{D} \cdot GMIN,} & {{if} V_{D} \geq  3\frac{NkT}{q}} \ { IS_{eff}\left\lbrack {1 + \left( \frac{3NkT}{qV_{D}e})^{3} \right.} \right\rbrack + V_{D} \cdot GMIN,} & {{if}  BV_{eff} < V_{D} <  3\frac{NkT}{q}} \ { IS_{eff}\left( e^{\frac{ q({BV_{eff} + V_{D}})}{NkT}} \right) + V_{D} \cdot GMIN,} & {{if} V_{D} \leq  BV_{eff}} \ \end{cases}} & \ \end{array}]
Two secondary effects are modelled if the appropriate parameters (see table Junction DC parameters) are given: Recombination current and bottom and sidewall tunnel current.
The breakdown region must be described with more depth since the breakdown is not modeled physically. As written before, the breakdown modeling is based on two model parameters: the `nominal breakdown voltage' bv and the current at the onset of breakdown ibv. For the diode model to be consistent, the current value cannot be arbitrarily chosen, since the reverse bias and breakdown regions must match. When the diode enters breakdown region from reverse bias, the current is calculated using the formula
1
if you look at the source code in file diotemp.c you will discover that the exponential relation is replaced with a first order Taylor series expansion.
:
[\begin{array}{ll} {I_{bdwn} =  IS_{eff}\left( {e^{\frac{ q{\lbrack font\ rm\ \lbrack char\ B\ mathalpha\rbrack\lbrack char\ V\ mathalpha\rbrack\rbrack}}{NkT}}  1} \right)} & \ \end{array}]
The computed current is necessary to adjust the breakdown voltage making the two regions match. The algorithm is a little bit convoluted and only a brief description is given here:
if (IBV_{eff} < I_{bdwn}) then
(\begin{array}{ll} {IBV_{eff} = I_{bdwn}} & \ {BV_{eff} = {\lbrack font\ rm\ \lbrack char\ B\ mathalpha\rbrack\lbrack char\ V\ mathalpha\rbrack\rbrack}} & \ \end{array})
else
(\begin{array}{ll} {BV_{eff} = {\lbrack font\ rm\ \lbrack char\ B\ mathalpha\rbrack\lbrack char\ V\ mathalpha\rbrack\rbrack}  {\lbrack font\ rm\ \lbrack char\ N\ mathalpha\rbrack\rbrack}V_{t}\ln\left( \frac{IBV_{eff}}{I_{bdwn}} \right)} & \ \end{array})
Algorithm 7.1: Diode breakdown current calculation
Most real diodes shows a current increase that, at high current levels, does not follow the exponential relationship given above. This behavior is due to high level of carriers injected into the junction. High injection effects (as they are called) are modeled with ik and ikr.
[\begin{array}{ll} {I_{Deff} = \begin{cases} {\frac{I_{D}}{1 + \sqrt{\frac{I_{D}}{IK_{eff}}}},} & {{if} V_{D} \geq  3\frac{NkT}{q}} \ {\frac{I_{D}}{1 + \sqrt{\frac{I_{D}}{IKR_{eff}}}},} & {otherwise.} \ \end{cases}} & \ \end{array}]
Diode capacitance is divided into two different terms:
 Depletion capacitance
 Diffusion capacitance
Depletion capacitance is composed by two different contributes, one associated to the bottom of the junction (bottomwall depletion capacitance) and the other to the periphery (sidewall depletion capacitance). The basic equations are:
[C_{Diode} = C_{diffusion} + C_{depletion}]
Where the depletion capacitance is defined as:
[C_{depletion} = C_{depl_{bw}} + C_{depl_{sw}}]
The diffusion capacitance, due to the injected minority carriers, is modeled with the transit time** tt**:
[C_{diffusion} = {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\rbrack}\frac{\partial I_{Deff}}{\partial V_{D}}]
The depletion capacitance is more complex to model, since the function used to approximate it diverges when the diode voltage become greater than the junction builtin potential. To avoid function divergence, the capacitance function is approximated with a linear extrapolation for applied voltage greater than a fraction of the junction builtin potential.
[\begin{array}{llll} C_{depl_{bw}} & = & \begin{cases} {CJ_{eff}\left( 1  \frac{V_{D}}{\lbrack font\ rm\ \lbrack char\ V\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack})^{ {\lbrack font\ rm\ \lbrack char\ M\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack}}, \right.} & {{if} V_{D} < {\lbrack font\ rm\ \lbrack char\ F\ mathalpha\rbrack\lbrack char\ C\ mathalpha\rbrack\rbrack} \cdot {\lbrack font\ rm\ \lbrack char\ V\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack}} \ {CJ_{eff}\frac{1  {\lbrack font\ rm\ \lbrack char\ F\ mathalpha\rbrack\lbrack char\ C\ mathalpha\rbrack\rbrack}\left( {1 + {\lbrack font\ rm\ \lbrack char\ M\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack}I} \right) + {\lbrack font\ rm\ \lbrack char\ M\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack}\frac{V_{D}}{\lbrack font\ rm\ \lbrack char\ V\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack}}{\left( 1  {\lbrack font\ rm\ \lbrack char\ F\ mathalpha\rbrack\lbrack char\ C\ mathalpha\rbrack\rbrack})^{({1 + {\lbrack font\ rm\ \lbrack char\ M\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack}})} \right.},} & {{otherwise}.} \ \end{cases} & \ \end{array}]
[\begin{array}{ll} {C_{depl_{sw}} = \begin{cases} {CJP_{eff}\left( 1  \frac{V_{D}}{\lbrack font\ rm\ \lbrack char\ P\ mathalpha\rbrack\lbrack char\ H\ mathalpha\rbrack\lbrack char\ P\ mathalpha\rbrack\rbrack})^{ {\lbrack font\ rm\ \lbrack char\ M\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\lbrack char\ W\ mathalpha\rbrack\rbrack}}, \right.} & {if V_{D} < {\lbrack font\ rm\ \lbrack char\ F\ mathalpha\rbrack\lbrack char\ C\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\rbrack} \cdot {\lbrack font\ rm\ \lbrack char\ P\ mathalpha\rbrack\lbrack char\ H\ mathalpha\rbrack\lbrack char\ P\ mathalpha\rbrack\rbrack}} \ {CJP_{eff}\frac{1  {\lbrack font\ rm\ \lbrack char\ F\ mathalpha\rbrack\lbrack char\ C\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\rbrack}\left( {1 + {\lbrack font\ rm\ \lbrack char\ M\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\lbrack char\ W\ mathalpha\rbrack\rbrack}} \right) + {\lbrack font\ rm\ \lbrack char\ M\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\lbrack char\ W\ mathalpha\rbrack\rbrack} \cdot \frac{V_{D}}{\lbrack font\ rm\ \lbrack char\ P\ mathalpha\rbrack\lbrack char\ H\ mathalpha\rbrack\lbrack char\ P\ mathalpha\rbrack\rbrack}}{\left( 1  {\lbrack font\ rm\ \lbrack char\ F\ mathalpha\rbrack\lbrack char\ C\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\rbrack})^{({1 + {\lbrack font\ rm\ \lbrack char\ M\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\lbrack char\ W\ mathalpha\rbrack\rbrack}})} \right.},} & {{otherwise}.} \ \end{cases}} & \ \end{array}]
Temperature dependence
The temperature affects many of the parameters in the equations above, and the following equations show how. One of the most significant parameters that varies with the temperature for a semiconductor is the bandgap energy:
[\begin{array}{ll} {EG_{nom} = 1.16  7.02e^{ 4}\frac{{\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack}^{2}}{{\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} + 1108.0}} & \ \end{array}]
[\begin{array}{ll} {EG\left( T \right) = 1.16  7.02e^{ 4}\frac{T^{2}}{{\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} + 1108.0}} & \ \end{array}]
The leakage current temperature's dependence is:
[\begin{array}{ll} {IS\left( T \right) = {\lbrack font\ rm\ \lbrack char\ I\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\rbrack} e^{\frac{logfactor}{\lbrack font\ rm\ \lbrack char\ N\ mathalpha\rbrack\rbrack}}} & \ \end{array}]
[\begin{array}{ll} {JSW\left( T \right) = {\lbrack font\ rm\ \lbrack char\ J\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\lbrack char\ W\ mathalpha\rbrack\rbrack} e^{\frac{logfactor}{\lbrack font\ rm\ \lbrack char\ N\ mathalpha\rbrack\rbrack}}} & \ \end{array}]
where `logfactor' is defined as
[\begin{array}{ll} {logfactor = \frac{\lbrack font\ rm\ \lbrack char\ E\ mathalpha\rbrack\lbrack char\ G\ mathalpha\rbrack\rbrack}{V_{t}\left( {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right)}  \frac{\lbrack font\ rm\ \lbrack char\ E\ mathalpha\rbrack\lbrack char\ G\ mathalpha\rbrack\rbrack}{V_{t}\left( T \right)} + {\lbrack font\ rm\ \lbrack char\ X\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\lbrack char\ I\ mathalpha\rbrack\rbrack}\ln\left( \frac{T}{\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right)} & \ \end{array}]
The contact potentials (bottomwall an sidewall) temperature dependence is:
[\begin{array}{ll} {VJ\left( T \right) = {\lbrack font\ rm\ \lbrack char\ V\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack}\left( \frac{T}{\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right)  V_{t}\left( T \right)\left\lbrack {3 \cdot \ln\left( \frac{T}{\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right) + \frac{\lbrack font\ rm\ \lbrack char\ E\ mathalpha\rbrack\lbrack sub\ \lbrack char\ G\ mathalpha\rbrack\ \lbrack char\ n\ mathalpha\rbrack\lbrack char\ o\ mathalpha\rbrack\lbrack char\ m\ mathalpha\rbrack\rbrack\rbrack}{V_{t}\left( {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right)}  \frac{\lbrack font\ rm\ \lbrack char\ E\ mathalpha\rbrack\lbrack char\ G\ mathalpha\rbrack\lbrack char\ (\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\lbrack char\ )\ mathalpha\rbrack\rbrack}{V_{t}\left( T \right)}} \right\rbrack} & \ \end{array}]
[\begin{array}{ll} {PHP\left( T \right) = {\lbrack font\ rm\ \lbrack char\ P\ mathalpha\rbrack\lbrack char\ H\ mathalpha\rbrack\lbrack char\ P\ mathalpha\rbrack\rbrack}\left( \frac{T}{\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right)  V_{t}\left( T \right)\left\lbrack {3 \cdot \ln\left( \frac{T}{\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right) + \frac{\lbrack font\ rm\ \lbrack char\ E\ mathalpha\rbrack\lbrack sub\ \lbrack char\ G\ mathalpha\rbrack\ \lbrack char\ n\ mathalpha\rbrack\lbrack char\ o\ mathalpha\rbrack\lbrack char\ m\ mathalpha\rbrack\rbrack\rbrack}{V_{t}\left( {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack} \right)}  \frac{\lbrack font\ rm\ \lbrack char\ E\ mathalpha\rbrack\lbrack char\ G\ mathalpha\rbrack\lbrack char\ (\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\lbrack char\ )\ mathalpha\rbrack\rbrack}{V_{t}\left( T \right)}} \right\rbrack} & \ \end{array}]
The depletion capacitances temperature dependence is:
[\begin{array}{ll} {CJ\left( T \right) = {\lbrack font\ rm\ \lbrack char\ C\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack}\left\lbrack {1 + {\lbrack font\ rm\ \lbrack char\ M\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack}\left( {4.0e^{ 4}\left( {T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack}} \right)  \frac{VJ\left( T \right)}{\lbrack font\ rm\ \lbrack char\ V\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack} + 1} \right)} \right\rbrack} & \ \end{array}]
[\begin{array}{ll} {CJSW\left( T \right) = {\lbrack font\ rm\ \lbrack char\ C\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\lbrack char\ W\ mathalpha\rbrack\rbrack}\left\lbrack {1 + {\lbrack font\ rm\ \lbrack char\ M\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\lbrack char\ W\ mathalpha\rbrack\rbrack}\left( {4.0e^{ 4}\left( {T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack}} \right)  \frac{PHP\left( T \right)}{\lbrack font\ rm\ \lbrack char\ P\ mathalpha\rbrack\lbrack char\ H\ mathalpha\rbrack\lbrack char\ P\ mathalpha\rbrack\rbrack} + 1} \right)} \right\rbrack} & \ \end{array}]
The transit time temperature dependence is:
[\begin{array}{ll} {TT\left( T \right) = {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\rbrack}\left( 1 + {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\lbrack char\ 1\ mathalpha\rbrack\rbrack}\left( {T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack}} \right) + {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\lbrack char\ T\ mathalpha\rbrack\lbrack char\ 2\ mathalpha\rbrack\rbrack}\left( {T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack})^{2}} \right) \right.} & \ \end{array}]
The junction grading coefficient temperature dependence is:
[\begin{array}{ll} {MJ\left( T \right) = {\lbrack font\ rm\ \lbrack char\ M\ mathalpha\rbrack\lbrack char\ J\ mathalpha\rbrack\rbrack}\left( 1 + {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\lbrack char\ 1\ mathalpha\rbrack\rbrack}\left( {T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack}} \right) + {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\lbrack char\ 2\ mathalpha\rbrack\rbrack}\left( {T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack})^{2}} \right) \right.} & \ \end{array}]
The series resistance temperature dependence is:
[\begin{array}{ll} {RS\left( T \right) = {\lbrack font\ rm\ \lbrack char\ R\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\rbrack}\left( 1 + {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ R\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\rbrack}\left( {T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack}} \right) + {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ R\ mathalpha\rbrack\lbrack char\ S\ mathalpha\rbrack\lbrack char\ 2\ mathalpha\rbrack\rbrack}\left( {T  {\lbrack font\ rm\ \lbrack char\ T\ mathalpha\rbrack\lbrack char\ N\ mathalpha\rbrack\lbrack char\ O\ mathalpha\rbrack\lbrack char\ M\ mathalpha\rbrack\rbrack})^{2}} \right) \right.} & \ \end{array}]
Noise model
The diode has three noise contribution, one due to the presence of the parasitic resistance rs and the other two (shot and flicker) due to the pn junction.
The thermal noise due to the parasitic resistance is:
[\begin{array}{ll} {\overline{i_{RS}^{2}} = \frac{4kT\Delta f}{RS}} & \ \end{array}]
The shot and flicker noise contributions are:
[\begin{array}{ll} {\overline{i_{d}^{2}} = 2qI_{D}\Delta f + \frac{KF \cdot I_{D}^{AF}}{f}\Delta f} & \ \end{array}]
BJTs
Bipolar Junction Transistors (BJTs)
General form:
QXXXXXXX nc nb ne <ns> mname <area=val> <areac=val>
+ <areab=val> <m=val> <off> <ic=vbe,vce> <temp=val>
+ <dtemp=val>
Examples:
Q23 10 24 13 QMOD IC=0.6, 5.0
Q50A 11 26 4 20 MOD1
nc,** nb**, and ne are the collector, base, and emitter nodes, respectively. ns is the (optional) substrate node. When unspecified, ground is used. mname is the model name, area, areab, areac are the area factors (emitter, base and collector respectively), and off indicates an (optional) initial condition on the device for the dc analysis. If the area factor is omitted, a value of 1.0 is assumed.
The (optional) initial condition specification using ic=vbe,vce is intended for use with the uic option on a .tran control line, when a transient analysis is desired to start from other than the quiescent operating point. See the .ic control line description for a better way to set transient initial conditions. The (optional) temp value is the temperature where this device is to operate, and overrides the temperature specification on the .option control line. Using the dtemp option one can specify the instance's temperature relative to the circuit temperature.
BJT Models (NPN/PNP)
Ngspice provides three BJT device models, which are selected by the .model card.
.model QMOD1 BJT level=2
This is the minimal version, further optional parameters listed in the table below may replace the ngspice default parameters. The** level** keyword specifies the model to be used:
 level=1: This is the original SPICE BJT model, and it is the default model if the level keyword is not specified on the .model line.
 level=2: This is a modified version of the original SPICE BJT that models both vertical and lateral devices and includes temperature corrections of collector, emitter and base resistors.
 level=4: Advanced VBIC model (see http://www.designersguide.org/VBIC/ for details)
The bipolar junction transistor model in ngspice is an adaptation of the integral charge control model of Gummel and Poon. This modified GummelPoon model extends the original model to include several effects at high bias levels. The model automatically simplifies to the simpler EbersMoll model when certain parameters are not specified. The parameter names used in the modified GummelPoon model have been chosen to be more easily understood by the user, and to reflect better both physical and circuit design thinking.
The dc model is defined by the parameters is, bf, nf, ise, ikf, and ne, which determine the forward current gain characteristics, is, br, nr, isc, ikr, and nc, which determine the reverse current gain characteristics, and vaf and var, which determine the output conductance for forward and reverse regions.
The level 1 model has among the standard temperature parameters an extension compatible with most foundry provided process design kits (see parameter table below tlev).
The level 1 and 2 models include the substrate saturation current iss. Three ohmic resistances rb, rc, and re are included, where rb can be high current dependent. Base charge storage is modeled by forward and reverse transit times, tf and tr, where the forward transit time tf can be bias dependent if desired. Nonlinear depletion layer capacitances are defined with cje, vje, and nje for the BE junction, cjc, vjc, and njc for the BC junction and cjs, vjs, and mjs for the CS (collectorsubstrate) junction.
The level 1 and 2 model support a substrate capacitance that is connected to the device's base or collector, to model lateral or vertical devices dependent on the parameter subs. The temperature dependence of the saturation currents, is and iss (for the level 2 model), is determined by the energygap, eg, and the saturation current temperature exponent, xti.
In the new model, additional base current temperature dependence is modeled by the beta temperature exponent xtb. The values specified are assumed to have been measured at the temperature tnom, which can be specified on the .options control line or overridden by a specification on the .model line.
The level 4 model (VBIC) has the following improvements beyond the GP models: improved Early effect modeling, quasisaturation modeling, parasitic substrate transistor modeling, parasitic fixed (oxide) capacitance modeling, includes an avalanche multiplication model, improved temperature modeling, base current is decoupled from collector current, electrothermal modeling, smooth and continuous mode.
The BJT parameters used in the modified GummelPoon model are listed below. The parameter names used in earlier versions of SPICE2 are still accepted.
GummelPoon BJT Parameters (incl. model extensions)
Name

Parameters

Units

Default

Example

Scale factor

SUBS

Substrate connection: for vertical geometry, 1 for lateral geometry (level 2 only).

1


IS

Transport saturation current.

A

1.0e16

1.0e15

area

ISS

Reverse saturation current, substratetocollector for vertical device or substratetobase for lateral (level 2 only).

A

1.0e16

1.0e15

area

BF

Ideal maximum forward beta.



100

100


NF

Forward current emission coefficient.



1.0

1


VAF (VA)

Forward Early voltage.

V

∞

200


IKF

Corner for forward beta current rolloff.

A

∞

0.01

area

NKF

High current Beta rolloff exponent



0.5

0.58


ISE

BE leakage saturation current.

A

0.0

1e13

area

NE

BE leakage emission coefficient.



1.5

2


BR

Ideal maximum reverse beta.



1

0.1


NR

Reverse current emission coefficient.



1

1


VAR (VB)

Reverse Early voltage.

V

∞

200


IKR

Corner for reverse beta high current rolloff.

A

∞

0.01

area

ISC

BC leakage saturation current (area is `areab' for vertical devices and `areac' for lateral).

A

0.0

1e13

area

NC

BC leakage emission coefficient.



2

1.5


RB

Zero bias base resistance.

Ω

0

100

area

IRB

Current where base resistance falls halfway to its min value.

A

∞

0.1

area

RBM

Minimum base resistance at high currents.

Ω

RB

10

area

RE

Emitter resistance.

Ω

0

1

area

RC

Collector resistance.

Ω

0

10

area

CJE

BE zerobias depletion capacitance.

F

0

2pF

area

VJE (PE)

BE builtin potential.

V

0.75

0.6


MJE (ME)

BE junction exponential factor.



0.33

0.33


TF

Ideal forward transit time.

sec

0

0.1ns


XTF

Coefficient for bias dependence of TF.



0


VTF

Voltage describing VBC dependence of TF.

V

∞


ITF

Highcurrent parameter for effect on TF.

A

0



area

PTF

Excess phase at freq=$\frac{1}{2\pi TF}$ Hz.

deg

0


CJC

BC zerobias depletion capacitance (area is `areab' for vertical devices and `areac' for lateral).

F

0

2pF

area

VJC (PC)

BC builtin potential.

V

0.75

0.5


MJC

BC junction exponential factor.



0.33

0.5


XCJC

Fraction of BC depletion capacitance connected to internal base node.



1


TR

Ideal reverse transit time.

sec

0

10ns


CJS

Zerobias collectorsubstrate capacitance (area is `areac' for vertical devices and `areab' for lateral).

F

0

2pF

area

VJS (PS)

Substrate junction builtin potential.

V

0.75


MJS (MS)

Substrate junction exponential factor.



0

0.5


XTB

Forward and reverse beta temperature exponent.



0


EG

Energy gap for temperature effect on IS.

eV

1.11


XTI

Temperature exponent for effect on IS.



3


KF

Flickernoise coefficient.



0


AF

Flickernoise exponent.



1


FC

Coefficient for forwardbias depletion capacitance formula.



0.5

0


TNOM (TREF)

Parameter measurement temperature.

C

27

50


TLEV

BJT temperature equation selector



0


TLEVC

BJT capac. temperature equation selector



0


TRE1

1st order temperature coefficient for RE.

$\frac{1}{C}$

0.0

1e3


TRE2

2nd order temperature coefficient for RE.

$\frac{1}{C^{2}}$

0.0

1e5


TRC1

1st order temperature coefficient for RC .

$\frac{1}{C}$

0.0

1e3


TRC2

2nd order temperature coefficient for RC.

$\frac{1}{C^{2}}$

0.0

1e5


TRB1

1st order temperature coefficient for RB.

$\frac{1}{C}$

0.0

1e3


TRB2

2nd order temperature coefficient for RB.

$\frac{1}{C^{2}}$

0.0

1e5


TRBM1

1st order temperature coefficient for RBM

$\frac{1}{C}$

0.0

1e3


TRBM2

2nd order temperature coefficient for RBM

$\frac{1}{C^{2}}$

0.0

1e5


TBF1

1st order temperature coefficient for BF

$\frac{1}{C}$

0.0

1e3


TBF2

2nd order temperature coefficient for BF

$\frac{1}{C^{2}}$

0.0

1e5


TBR1

1st order temperature coefficient for BR

$\frac{1}{C}$

0.0

1e3


TBR2

2nd order temperature coefficient for BR

$\frac{1}{C^{2}}$

0.0

1e5


TIKF1

1st order temperature coefficient for IKF

$\frac{1}{C}$

0.0

1e3


TIKF2

2nd order temperature coefficient for IKF

$\frac{1}{C^{2}}$

0.0

1e5


TIKR1

1st order temperature coefficient for IKR

$\frac{1}{C}$

0.0

1e3


TIKR2

2nd order temperature coefficient for IKR

$\frac{1}{C^{2}}$

0.0

1e5


TIRB1

1st order temperature coefficient for IRB

$\frac{1}{C}$

0.0

1e3


TIRB2

2nd order temperature coefficient for IRB

$\frac{1}{C^{2}}$

0.0

1e5


TNC1

1st order temperature coefficient for NC

$\frac{1}{C}$

0.0

1e3


TNC2

2nd order temperature coefficient for NC

$\frac{1}{C^{2}}$

0.0

1e5


TNE1

1st order temperature coefficient for NE

$\frac{1}{C}$

0.0

1e3


TNE2

2nd order temperature coefficient for NE

$\frac{1}{C^{2}}$

0.0

1e5


TNF1

1st order temperature coefficient for NF

$\frac{1}{C}$

0.0

1e3


TNF2

2nd order temperature coefficient for NF

$\frac{1}{C^{2}}$

0.0

1e5


TNR1

1st order temperature coefficient for IKF

$\frac{1}{C}$

0.0

1e3


TNR2

2nd order temperature coefficient for IKF

$\frac{1}{C^{2}}$

0.0

1e5


TVAF1

1st order temperature coefficient for VAF

$\frac{1}{C}$

0.0

1e3


TVAF2

2nd order temperature coefficient for VAF

$\frac{1}{C^{2}}$

0.0

1e5


TVAR1

1st order temperature coefficient for VAR

$\frac{1}{C}$

0.0

1e3


TVAR2

2nd order temperature coefficient for VAR

$\frac{1}{C^{2}}$

0.0

1e5


CTC

1st order temperature coefficient for CJC

$\frac{1}{C}$

0.0

1e3


CTE

1st order temperature coefficient for CJE

$\frac{1}{C}$

0.0

1e3


CTS

1st order temperature coefficient for CJS

$\frac{1}{C}$

0.0

1e3


TVJC

1st order temperature coefficient for VJC

$\frac{1}{C^{2}}$

0.0

1e5


TVJE

1st order temperature coefficient for VJE

$\frac{1}{C}$

0.0

1e3


TITF1

1st order temperature coefficient for ITF

$\frac{1}{C}$

0.0

1e3


TITF2

2nd order temperature coefficient for ITF

$\frac{1}{C^{2}}$

0.0

1e5


TTF1

1st order temperature coefficient for TF

$\frac{1}{C}$

0.0

1e3


TTF2

2nd order temperature coefficient for TF

$\frac{1}{C^{2}}$

0.0

1e5


TTR1

1st order temperature coefficient for TR

$\frac{1}{C}$

0.0

1e3


TTR2

2nd order temperature coefficient for TR

$\frac{1}{C^{2}}$

0.0

1e5


TMJE1

1st order temperature coefficient for MJE

$\frac{1}{C}$

0.0

1e3


TMJE2

2nd order temperature coefficient for MJE

$\frac{1}{C^{2}}$

0.0

1e5


TMJC1

1st order temperature coefficient for MJC

$\frac{1}{C}$

0.0

1e3


TMJC2

2nd order temperature coefficient for MJC

$\frac{1}{C^{2}}$

0.0

1e5

JFETs
Junction FieldEffect Transistors (JFETs)
General form:
JXXXXXXX nd ng ns mname <area> <off> <ic=vds,vgs> <temp=t>
Examples:
J1 7 2 3 JM1 OFF
nd, ng, and ns are the drain, gate, and source nodes, respectively. mname is the model name, area is the area factor, and off indicates an (optional) initial condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification, using ic=VDS,VGS is intended for use with the uic option on the .TRAN control line, when a transient analysis is desired starting from other than the quiescent operating point. See the .ic control line for a better way to set initial conditions. The (optional) temp value is the temperature where this device is to operate, and overrides the temperature specification on the .option control line.
JFET Models (NJF/PJF)
JFET level 1 model with Parker Skellern modification
The level 1 JFET model is derived from the FET model of Shichman and Hodges. The dc characteristics are defined by the parameters VTO and BETA, which determine the variation of drain current with gate voltage, LAMBDA, which determines the output conductance, and IS, the saturation current of the two gate junctions. Two ohmic resistances, RD and RS, are included.
[\begin{array}{ll} {vgst = vgs  VTO} & \ \end{array}]
[\begin{array}{ll} {\beta_{p} = BETA\left( {1 + LAMBDA vds} \right)} & \ \end{array}]
[\begin{array}{ll} {bfac = \frac{1  B}{PB  VTO}} & \ \end{array}]
[\begin{array}{ll} {I_{Drain} = \begin{cases} {vds \cdot GMIN,} & {{if} vgst \leq 0} \ {\beta_{p} vds\left( {vds\left( {bfac vds  B} \right) vgst\left( {2B + 3bfac\left( {vgst  vds} \right)} \right)} \right) + vds \cdot GMIN,} & {{if} vgst \geq vds} \ {\beta_{p} vgst^{2}\left( {B + vgst bfac} \right) + vds \cdot GMIN,} & {{if} vgst < vds} \ \end{cases}} & \ \end{array}]
Note that in Spice3f and later, the fitting parameter B has been added by Parker and Skellern. For details, see [9]. If parameter B is set to 1 equation above simplifies to
[\begin{array}{ll} {I_{Drain} = \begin{cases} {vds \cdot GMIN,} & {{if} vgst \leq 0} \ {\beta_{p} vds\left( {2vgst  vds} \right) + vds \cdot GMIN,} & {{if} vgst \geq vds} \ {\beta_{p} vgst^{2} + vds \cdot GMIN,} & {{if} vgst < vds} \ \end{cases}} & \ \end{array}]
Charge storage is modeled by nonlinear depletion layer capacitances for both gate junctions, which vary as the ( \frac{1}{2}) power of junction voltage and are defined by the parameters CGS, CGD, and PB.
Name

Parameter

Units

Default

Example

Scaling factor

VTO

Threshold voltage V_{T0}

V

2.0

2.0


BETA

Transconductance parameter (β)

$\frac{A}{V^{"}}$

1.0e4

1.0e3

area

LAMBDA

Channellength modulation parameter (λ)

$\frac{1}{V}$

0

1.0e4


RD

Drain ohmic resistance

Ω

0

100

area

RS

Source ohmic resistance

Ω

0

100

area

CGS

Zerobias GS junction capacitance C_{gs}

F

0

5pF

area

CGD

Zerobias GD junction capacitance C_{gd}

F

0

1pF

area

PB

Gate junction potential

V

1

0.6


IS

Gate saturation current I_{S}

A

1.0e14

1.0e14

area

B

Doping tail parameter



1

1.1


KF

Flicker noise coefficient



0


AF

Flicker noise exponent



1


NLEV

Noise equation selector



1

3


GDSNOI

Channel noise coefficient for nlev=3

1.0

2.0


FC

Coefficient for forwardbias depletion capacitance formula

0.5


TNOM

Parameter measurement temperature

C

27

50


TCV

Threshold voltage temperature coefficient

$\frac{1}{C}$

0.0

0.1


BEX

Mobility temperature exponent



0.0

1.1

Additional to the standard thermal and flicker noise model an alternative thermal channel noise model is implemented and is selectable by setting NLEV parameter to 3. This follows in a correct channel thermal noise in the linear region.
[\begin{array}{ll} {S_{noise} = \frac{2}{3} 4kT \cdot BETA \cdot Vgst\frac{\left( {1 + \alpha + \alpha^{2}} \right)}{1 + \alpha}GDSNOI} & \ \end{array}]
with
[\begin{array}{ll} {\alpha = \begin{cases} {1  \frac{vds}{vgs  VTO},} & {{if} vgs  VTO \geq vds} \ {0,} & {else} \ \end{cases}} & \ \end{array}]
JFET level 2 Parker Skellern model
The level 2 model is an improvement to level 1. Details are available from Macquarie University. Some important items are:
 The description maintains strict continuity in its highorder derivatives, which is essential for prediction of distortion and intermodulation.
 Frequency dependence of output conductance and transconductance is described as a function of bias.
 Both draingate and sourcegate potentials modulate the pinchoff potential, which is consistent with Sparameter and pulsedbias measurements.
 Selfheating varies with frequency.
 Extreme operating regions  subthreshold, forward gate bias, controlled resistance, and breakdown regions  are included.
 Parameters provide independent fitting to all operating regions. It is not necessary to compromise one region in favor of another.
 Strict drainsource symmetry is maintained. The transition during drainsource potential reversal is smooth and continuous.
The model equations are described in this pdf document and in [19].
Name

Description

Units

Default

ID

Device IDText

Text

PF1

ACGAM

Capacitance modulation



0

BETA

Linearregion transconductance scale



10^{−4}

CGD

Zerobias gatesource capacitance

F

0

CGS

Zerobias gatedrain capacitance

F

0

DELTA

Thermal reduction coefficient

$\frac{1}{W}$

0

FC

Forward bias capacitance parameter



0.5

HFETA

Highfrequency VGS feedback parameter



0

HFE1

HFGAM modulation by VGD

$\frac{1}{V}$

0

HFE2

HFGAM modulation by VGS

$\frac{1}{V}$

0

HFGAM

Highfrequency VGD feedback parameter



0

HFG1

HFGAM modulation by VSG

$\frac{1}{V}$

0

HFG2

HFGAM modulation by VDG

$\frac{1}{V}$

0

IBD

Gatejunction breakdown current

A

0

IS

Gatejunction saturation current

A

10^{−14}

LFGAM

Lowfrequency feedback parameter



0

LFG1

LFGAM modulation by VSG

$\frac{1}{V}$

0

LFG2

LFGAM modulation by VDG

$\frac{1}{V}$

0

MVST

Subthreshold modulation

$\frac{1}{V}$

0

N

Gatejunction ideality factor



1

P

Linearregion powerlaw exponent



2

Q

Saturatedregion powerlaw exponent



2

RS

Source ohmic resistance

Ω

0

RD

Drain ohmic resistance

Ω

0

TAUD

Relaxation time for thermal reduction

s

0

TAUG

Relaxation time for gamma feedback

s

0

VBD

Gatejunction breakdown potential

V

1

VBI

Gatejunction potential

V

1

VST

Subthreshold potential

V

0

VTO

Threshold voltage

V

2.0

XC

Capacitance pinchoff reduction factor



0

XI

Saturationknee potential factor



1000

Z

Knee transition parameter



0.5

RG

Gate ohmic resistance

Ω

0

LG

Gate inductance

H

0

LS

Source inductance

H

0

LD

Drain inductance

H

0

CDSS

Fixed Drainsource capacitance

F

0

AFAC

Gatewidth scale factor



1

NFING

Number of gate fingers scale factor



1

TNOM

Nominal Temperature (Not implemented)

K

300 K

TEMP

Temperature

K

300 K

MESFETs
MESFETs
General form:
ZXXXXXXX ND NG NS MNAME <AREA> <OFF> <IC=VDS, VGS>
Examples:
Z1 7 2 3 ZM1 OFF
MESFET Models (NMF/PMF)
Model by Statz e.a.
The MESFET model level 1 is derived from the GaAs FET model of Statz et al. as described in [11]. The dc characteristics are defined by the parameters VTO, B, and BETA, which determine the variation of drain current with gate voltage, ALPHA, which determines saturation voltage, and LAMBDA, which determines the output conductance. The formula are given by:
[\begin{array}{ll} {I_{d} = \begin{cases} {\frac{B\left( V_{gs}  V_{T})^{2} \right.}{1 + b\left( {V_{gs}  V_{T}} \right)}\left {1  \left {1  A\frac{V_{ds}}{3}} \right^{3}} \right\left( {1 + LV_{ds}} \right)} & {{for}0 < V_{ds} < \frac{3}{A}} \ {\frac{B\left( V_{gs}  V_{T})^{2} \right.}{1 + b\left( {V_{gs}  V_{T}} \right)}\left( {1 + LV_{ds}} \right)} & {{for}V > \frac{3}{A}} \ \end{cases}} & \ \end{array}]
Two ohmic resistances, rd and rs, are included. Charge storage is modeled by total gate charge as a function of gatedrain and gatesource voltages and is defined by the parameters cgs, cgd, and pb.
Name

Parameter

Units

Default

Example

Area

VTO

Pinchoff voltage

V

2.0

2.0


BETA

Transconductance parameter

$\frac{A}{V^{2}}$

1.0e4

1.0e3

*

B

Doping tail extending parameter

$\frac{1}{V}$

0.3

0.3

*

ALPHA

Saturation voltage parameter

$\frac{1}{V}$

2

2

*

LAMBDA

Channellength modulation parameter

$\frac{1}{V}$

0

1.0e4


RD

Drain ohmic resistance

Ω

0

100

*

RS

Source ohmic resistance

Ω

0

100

*

CGS

Zerobias GS junction capacitance

F

0

5pF

*

CGD

Zerobias GD junction capacitance

F

0

1pF

*

PB

Gate junction potential

V

1

0.6


KF

Flicker noise coefficient



0


AF

Flicker noise exponent



1


FC

Coefficient for forwardbias depletion capacitance formula



0.5

Device instance:
z1 2 3 0 mesmod area=1.4
Model:
.model mesmod nmf level=1 rd=46 rs=46 vt0=1.3
+ lambda=0.03 alpha=3 beta=1.4e3
Model by Ytterdal e.a.
level 2 (and levels 3,4) Copyright 1993: T. Ytterdal, K. Lee, M. Shur and T. A. Fjeldly
to be written
M. Shur, T.A. Fjeldly, T. Ytterdal, K. Lee, "Unified GaAs MESFET Model for Circuit Simulation", Int. Journal of High Speed Electronics, vol. 3, no. 2, pp. 201233, 1992
hfet1
level 5
to be written
no documentation available
hfet2
level6
to be written
no documentation available
MOSFETs
Ngspice supports all the original mosfet models present in SPICE3f5 and almost all the newer ones that have been published and made opensource. Both bulk and SOI (Silicon on Insulator) models are available. When compiled with the cider option, ngspice implements the four terminals numerical model that can be used to simulate a MOSFET (please refer to numerical modeling documentation for additional information and examples).
MOSFET devices
General form:
MXXXXXXX nd ng ns nb mname <m=val> <l=val> <w=val>
+ <ad=val> <as=val> <pd=val> <ps=val> <nrd=val>
+ <nrs=val> <off> <ic=vds, vgs, vbs> <temp=t>
Examples:
M1 24 2 0 20 TYPE1
M31 2 17 6 10 MOSN L=5U W=2U
M1 2 9 3 0 MOSP L=10U W=5U AD=100P AS=100P PD=40U PS=40U
Note the suffixes in the example: the suffix `u' specifies microns (1e6 (m)) and `p' sqmicrons (1e12 (m^{2})).
The instance card for MOS devices starts with the letter 'M'. nd, ng, ns, and nb are the drain, gate, source, and bulk (substrate) nodes, respectively. mname is the model name and m is the multiplicity parameter, which simulates `m' paralleled devices. All MOS models support the `m' multiplier parameter. Instance parameters l and w, channel length and width respectively, are expressed in meters. The areas of drain and source diffusions: ad and as, in squared meters ((m^{2})).
If any of l, w, ad, or as are not specified, default values are used. The use of defaults simplifies input file preparation, as well as the editing required if device geometries are to be changed. pd and ps are the perimeters of the drain and source junctions, in meters. nrd and nrs designate the equivalent number of squares of the drain and source diffusions; these values multiply the sheet resistance rsh specified on the .model control line for an accurate representation of the parasitic series drain and source resistance of each transistor. pd and ps default to 0.0 while nrd and nrs to 1.0. off indicates an (optional) initial condition on the device for dc analysis. The (optional) initial condition specification using ic=vds,vgs,vbs is intended for use with the uic option on the .tran control line, when a transient analysis is desired starting from other than the quiescent operating point. See the .ic control line for a better and more convenient way to specify transient initial conditions. The (optional) temp value is the temperature at which this device is to operate, and overrides the temperature specification on the .option control line.
The temperature specification is ONLY valid for level 1, 2, 3, and 6 MOSFETs, not for level 4 or 5 (BSIM) devices.
BSIM3 (v3.2 and v3.3.0), BSIM4 (v4.7 and v4.8) and BSIMSOI models are also supporting the instance parameter delvto and mulu0 for local mismatch and NBTI (negative bias temperature instability) modeling:
Name

Parameter

Units

Default

Example

delvto (delvt0)

Threshold voltage shift

V

0.0

0.07

mulu0

Lowfield mobility multiplier (U0)



1.0

0.9

MOSFET models (NMOS/PMOS)
MOSFET models are the central part of ngspice, probably because they are the most widely used devices in the electronics world. Ngspice provides all the MOSFETs implemented in the original Spice3f and adds several models developed by UC Berkeley's Device Group and other independent groups.
Each model is invoked with a .model card. A minimal version is:
.model MOSN NMOS level=8 version=3.3.0
The model name MOSN corresponds to the model name in the instance card (see 11.1). Parameter NMOS selects an nchannel device, PMOS would point to a pchannel transistor. The level and version parameters select the specific model. Further model parameters are optional and replace ngspice default values. Due to the large number of parameters (more than 100 for modern models), model cards may be stored in extra files and loaded into the netlist by the .include (2.6) command. Model cards are specific for a an IC manufacturing process and are typically provided by the IC foundry. Some generic parameter sets, not linked to a specific process, are made available by the model developers, e.g. UC Berkeley's Device Group for BSIM4 and BSIMSOI.
Ngspice provides several MOSFET device models, which differ in the formulation of the IV characteristic, and are of varying complexity. Models available are listed in table 11.1. Current models for IC design are BSIM3 (11.2.10, down to channel length of 0.25 µm), BSIM4 (11.2.11, below 0.25 µm), BSIMSOI (11.2.13, silicononinsulator devices), HiSIM2 and HiSIM_HV (11.2.15, surface potential models for standard and high voltage/high power MOS devices).
Level

Name

Model

Version

Developer

References

Notes

1

MOS1

ShichmanHodges



Berkeley

This is the classical quadratic model.


2

MOS2

GroveFrohman



Berkeley

Described in [2]


3

MOS3

Berkeley

A semiempirical model (see [1])


4

BSIM1

Berkeley

Described in [3]


5

BSIM2

Berkeley

Described in [5]


6

MOS6

Berkeley

Described in [2]


9

MOS9

Alan Gillespie


8, 49

BSIM3v0

3.0

Berkeley

extensions by Alan Gillespie


8, 49

BSIM3v1

3.1

Berkeley

extensions by Serban Popescu


8, 49

BSIM3v32

3.2  3.2.4

Berkeley

Multi version code


8, 49

BSIM3

3.3.0

Berkeley

Described in [13]


10, 58

B4SOI

4.3.1

Berkeley


14, 54

BSIM4v5

4.0  4.5

Berkeley

Multi version code


14, 54

BSIM4v6

4.6.5

Berkeley


14, 54

BSIM4v7

4.7.0

Berkeley


14, 54

BSIM4

4.8.1

Berkeley


44

EKV

EPFL

adms configured


45

PSP

1.0.2

Gildenblatt

adms configured


55

B3SOIFD

Berkeley


56

B3SOIDD

Berkeley


57

B3SOIPD

Berkeley


60

STAG

SOI3

Southampton


68

HiSIM2

2.8.0

Hiroshima


73

HiSIM_HV

1.2.4/2.2.0

Hiroshima

High Voltage Version for LDMOS

Table 11.1: MOSFET model summary
MOS Level 1
This model is also known as the `ShichmanHodges' model. This is the first model written and the one often described in the introductory textbooks for electronics. This model is applicable only to long channel devices. The use of Meyer's model for the CV part makes it non charge conserving.
MOS Level 2
This model tries to overcome the limitations of the Level 1 model addressing several shortchannel effects, like velocity saturation. The implementation of this model is complicated and this leads to many convergence problems. CV calculations can be done with the original Meyer model (non charge conserving).
MOS Level 3
This is a semiempirical model derived from the Level 2 model. In the 80s this model has often been used for digital design and, over the years, has proved to be robust. A discontinuity in the model with respect to the KAPPA parameter has been detected (see [10]). The supplied fix has been implemented in Spice3f2 and later. Since this fix may affect parameter fitting, the option badmos3 may be set to use the old implementation (see the section on simulation variables and the .options line). Ngspice level 3 implementation takes into account length and width mask adjustments (xl and xw) and device width narrowing due to diffusion (wd).
MOS Level 6
This model is described in [2]. The model can express the current characteristics of shortchannel MOSFETs at least down to 0.25 (\mu m) channellength, GaAs FET, and resistance inserted MOSFETs. The model evaluation time is about 1/3 of the evaluation time of the SPICE3 mos level 3 model. The model also enables analytical treatments of circuits in shortchannel region and makes up for a missing link between a complicated MOSFET current characteristics and circuit behaviors in the deep submicron region.
Notes on Level 16 models
The dc characteristics of the level 1 through level 3 MOSFETs are defined by the device parameters vto, kp, lambda, phi and gamma. These parameters are computed by ngspice if process parameters (nsub, tox, ...) are given, but users specified values always override. vto is positive (negative) for enhancement mode and negative (positive) for depletion mode Nchannel (Pchannel) devices.
Charge storage is modeled by three constant capacitors, cgso, cgdo, and cgbo, which represent overlap capacitances, by the nonlinear thinoxide capacitance that is distributed among the gate, source, drain, and bulk regions, and by the nonlinear depletionlayer capacitances for both substrate junctions divided into bottom and periphery, which vary as the mj and mjsw power of junction voltage respectively, and are determined by the parameters cbd, cbs, cj, cjsw, mj, mjsw and pb.
Charge storage effects are modeled by the piecewise linear voltagesdependent capacitance model proposed by Meyer. The thinoxide chargestorage effects are treated slightly different for the level 1 model. These voltagedependent capacitances are included only if tox is specified in the input description and they are represented using Meyer's formulation.
There is some overlap among the parameters describing the junctions, e.g. the reverse current can be input either as is (in A) or as js (in (\frac{A}{m^{2}})). Whereas the first is an absolute value the second is multiplied by ad and as to give the reverse current of the drain and source junctions respectively.
This methodology has been chosen since there is no sense in relating always junction characteristics with ad and as entered on the device line; the areas can be defaulted. The same idea applies also to the zerobias junction capacitances cbd and cbs (in F) on one hand, and cj (in (\frac{F}{m^{2}})) on the other.
The parasitic drain and source series resistance can be expressed as either rd and rs (in ohms) or rsh (in ohms/sq.), the latter being multiplied by the number of squares nrd and nrs input on the device line.
NGSPICE level 1, 2, 3 and 6 parameters
Name

Parameter

Units

Default

Example


LEVEL

Model index



1


VTO

Zerobias threshold voltage (V_{T0})

V

0.0

1.0

KP

Transconductance parameter

$\frac{A}{V^{2}}$

2.0e5

3.1e5

GAMMA

Bulk threshold parameter

$\sqrt{V}$

0.0

0.37

PHI

Surface potential (U)

V

0.6

0.65

LAMBDA

Channel length modulation (MOS1 and MOS2 only) (λ)

$\frac{1}{V}$

0.0

0.02

RD

Drain ohmic resistance

Ω

0.0

1.0

RS

Source ohmic resistance

Ω

0.0

1.0

CBD

Zerobias BD junction capacitance

F

0.0

20fF

CBS

Zerobias BS junction capacitance

F

0.0

20fF

IS

Bulk junction saturation current (I_{S})

A

1.0e14

1.0e15

PB

Bulk junction potential

V

0.8

0.87

CGSO

Gatesource overlap capacitance per meter channel width

$\frac{F}{m}$

0.0

4.0e11

CGDO

Gatedrain overlap capacitance per meter channel width

$\frac{F}{m}$

0.0

4.0e11

CGBO

Gatebulk overlap capacitance per meter channel width

$\frac{F}{m}$

0.0

2.0e11

RSH

Drain and source diffusion sheet resistance

$\frac{\Omega}{\square}$

0.0

10

CJ

Zerobias bulk junction bottom cap. per sqmeter of junction area

$\frac{F}{m^{2}}$

0.0

2.0e4

MJ

Bulk junction bottom grading coeff.



0.5

0.5

CJSW

Zerobias bulk junction sidewall cap. per meter of junction perimeter

$\frac{F}{m}$

0.0

1.0e9

MJSW

Bulk junction sidewall grading coeff.



$\begin{array}{ll}
0.50 & \left. \left( level \right.1 \right) \\
0.33 & \left. \left( level \right.2,3 \right) \\
\end{array}$


JS

Bulk junction saturation current


TOX

Oxide thickness

m

1.0e7

1.0e7

NSUB

Substrate doping

cm^{−3}

0.0

4.0e15

NSS

Surface state density

cm^{−2}

0.0

1.0e10

NFS

Fast surface state density

cm^{−2}

0.0

1.0e10

TPG

Type of gate material: +1 opp. to substrate, 1 same as substrate, 0 Al gate



1.0


XJ

Metallurgical junction depth

m

0.0

1M

LD

Lateral diffusion

m

0.0

0.8M

UO

Surface mobility

$\frac{cm^{2}}{V \cdot sec}$

600

700

UCRIT

Critical field for mobility degradation (MOS2 only)

$\frac{V}{cm}$

1.0e4

1.0e4

UEXP

Critical field exponent in mobility degradation (MOS2 only)



0.0

0.1

UTRA

Transverse field coeff. (mobility) (deleted for MOS2)



0.0

0.3

VMAX

Maximum drift velocity of carriers

$\frac{m}{s}$

0.0

5.0e4

NEFF

Total channelcharge (fixed and mobile) coefficient (MOS2 only)



1.0

5.0

KF

Flicker noise coefficient



0.0

1.0e26

AF

Flicker noise exponent



1.0

1.2

FC

Coefficient for forwardbias depletion capacitance formula



0.5


DELTA

Width effect on threshold voltage (MOS2 and MOS3)



0.0

1.0

THETA

Mobility modulation (MOS3 only)

$\frac{1}{V}$

0.0

0.1

ETA

Static feedback (MOS3 only)



0.0

1.0

KAPPA

Saturation field factor (MOS3 only)



0.2

0.5

TNOM

Parameter measurement temperature

C

27

50

MOS Level 9
Documentation is not available..
BSIM Models
Ngspice implements many of the BSIM models developed by Berkeley's BSIM group. BSIM stands for Berkeley ShortChannel IGFET Model and groups a class of models that is continuously updated. BSIM3 (11.2.10) and BSIM4 (11.2.11) are industry standards for CMOS processes down to 0.15 µm (BSIM3) and below (BSIM4), are very stable and are supported by model parameter sets from foundries all over the world. BSIM1 and BSIM2 are obsolete today.
In general, all parameters of BSIM models are obtained from process characterization, in particular level 4 and level 5 (BSIM1 and BSIM2) parameters can be generated automatically. J. Pierret [4] describes a means of generating a `process' file, and the program ngproc2mod provided with ngspice converts this file into a sequence of BSIM1 .model lines suitable for inclusion in an ngspice input file.
Parameters marked below with an * in the l/w column also have corresponding parameters with a length and width dependency. For example, vfb is the basic parameter with units of Volts, and lvfb and wvfb also exist and have units of Voltmeter.
The formula
[\begin{array}{ll} {P = P_{0} + \frac{P_{L}}{L_{\lbrack font\ rm\ \lbrack char\ e\ mathalpha\rbrack\lbrack char\ f\ mathalpha\rbrack\lbrack char\ f\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\lbrack char\ c\ mathalpha\rbrack\lbrack char\ t\ mathalpha\rbrack\lbrack char\ i\ mathalpha\rbrack\lbrack char\ v\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack}} + \frac{P_{W}}{W_{\lbrack font\ rm\ \lbrack char\ e\ mathalpha\rbrack\lbrack char\ f\ mathalpha\rbrack\lbrack char\ f\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\lbrack char\ c\ mathalpha\rbrack\lbrack char\ t\ mathalpha\rbrack\lbrack char\ i\ mathalpha\rbrack\lbrack char\ v\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack}}} & \ \end{array}]
is used to evaluate the parameter for the actual device specified with
[\begin{array}{ll} {L_{\lbrack font\ rm\ \lbrack char\ e\ mathalpha\rbrack\lbrack char\ f\ mathalpha\rbrack\lbrack char\ f\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\lbrack char\ c\ mathalpha\rbrack\lbrack char\ t\ mathalpha\rbrack\lbrack char\ i\ mathalpha\rbrack\lbrack char\ v\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack} = L_{\lbrack font\ rm\ \lbrack char\ i\ mathalpha\rbrack\lbrack char\ n\ mathalpha\rbrack\lbrack char\ p\ mathalpha\rbrack\lbrack char\ u\ mathalpha\rbrack\lbrack char\ t\ mathalpha\rbrack\rbrack}  DL} & \ \end{array}]
[\begin{array}{ll} {W_{\lbrack font\ rm\ \lbrack char\ e\ mathalpha\rbrack\lbrack char\ f\ mathalpha\rbrack\lbrack char\ f\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\lbrack char\ c\ mathalpha\rbrack\lbrack char\ t\ mathalpha\rbrack\lbrack char\ i\ mathalpha\rbrack\lbrack char\ v\ mathalpha\rbrack\lbrack char\ e\ mathalpha\rbrack\rbrack} = W_{\lbrack font\ rm\ \lbrack char\ i\ mathalpha\rbrack\lbrack char\ n\ mathalpha\rbrack\lbrack char\ p\ mathalpha\rbrack\lbrack char\ u\ mathalpha\rbrack\lbrack char\ t\ mathalpha\rbrack\rbrack}  DW} & \ \end{array}]
Note that unlike the other models in ngspice, the BSIM models are designed for use with a process characterization system that provides all the parameters, thus there are no defaults for the parameters, and leaving one out is considered an error. For an example set of parameters and the format of a process file, see the SPICE2 implementation notes [3]. For more information on BSIM2, see reference [5]. BSIM3 (11.2.10) and BSIM4 (11.2.11) represent state of the art for submicron and deep submicron IC design.
BSIM1 model (level 4)
BSIM1 model (the first is a long series) is an empirical model. Developers placed less emphasis on device physics and based the model on parametrical polynomial equations to model the various physical effects. This approach pays in terms of circuit simulation behavior but the accuracy degrades in the submicron region. A known problem of this model is the negative output conductance and the convergence problems, both related to poor behavior of the polynomial equations.
Ngspice BSIM (level 4) parameters
Name

Parameter

Units

l/w


VFB

Flatband voltage

V

*

PHI

Surface inversion potential

V

*

K1

Body effect coefficient

$\sqrt{V}$

*

K2

Drain/source depletion chargesharing coefficient



*

ETA

Zerobias draininduced barrierlowering coefficient



*

MUZ

Zerobias mobility

$\frac{cm^{2}}{V \cdot sec}$


DL

Shortening of channel

μm


DW

Narrowing of channel

μm


U0

Zerobias transversefield mobility degradation coefficient

$\frac{1}{V}$

*

U1

Zerobias velocity saturation coefficient

$\frac{\mu}{V}$

*

X2MZ

Sens. of mobility to substrate bias at v=0

$\frac{cm^{2}}{V^{2} \cdot sec}$

*

X2E

Sens. of draininduced barrier lowering effect to substrate bias

$\frac{1}{V}$

*

X3E

Sens. of draininduced barrier lowering effect to drain bias at V_{ds} = V_{dd}

$\frac{1}{V}$

*

X2U0

Sens. of transverse field mobility degradation effect to substrate bias

$\frac{1}{V^{2}}$

*

X2U1

Sens. of velocity saturation effect to substrate bias

$\frac{\mu m}{V^{2}}$

*

MUS

Mobility at zero substrate bias and at V_{ds} = V_{dd}

$\frac{cm^{2}}{V^{2}sec}$


X2MS

Sens. of mobility to substrate bias at V_{ds} = V_{dd}

$\frac{cm^{2}}{V^{2}sec}$

*

X3MS

Sens. of mobility to drain bias at V_{ds} = V_{dd}

$\frac{cm^{2}}{V^{2}sec}$

*

X3U1

Sens. of velocity saturation effect on drain bias at Vds=Vdd

$\frac{\mu m}{V^{2}}$

*

TOX

Gate oxide thickness

μm


TEMP

Temperature where parameters were measured

C


VDD

Measurement bias range

V


CGDO

Gatedrain overlap capacitance per meter channel width

$\frac{F}{m}$


CGSO

Gatesource overlap capacitance per meter channel width

$\frac{F}{m}$


CGBO

Gatebulk overlap capacitance per meter channel length

$\frac{F}{m}$


XPART

Gateoxide capacitancecharge model flag




N0

Zerobias subthreshold slope coefficient



*

NB

Sens. of subthreshold slope to substrate bias



*

ND

Sens. of subthreshold slope to drain bias



*

RSH

Drain and source diffusion sheet resistance

$\frac{\Omega}{\square}$


JS

Source drain junction current density

$\frac{A}{m^{2}}$


PB

Built in potential of source drain junction

V


MJ

Grading coefficient of source drain junction




PBSW

Built in potential of source, drain junction sidewall

V


MJSW

Grading coefficient of source drain junction sidewall




CJ

Source drain junction capacitance per unit area

$\frac{F}{m^{2}}$


CJSW

source drain junction sidewall capacitance per unit length

$\frac{F}{m}$


WDF

Source drain junction default width

m


DELL

Source drain junction length reduction

m

xpart = 0 selects a 40/60 drain/source charge partition in saturation, while xpart=1 selects a 0/100 drain/source charge partition. nd, ng, and ns are the drain, gate, and source nodes, respectively. mname is the model name, area is the area factor, and off indicates an (optional) initial condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification, using ic=vds,vgs is intended for use with the uic option on the .tran control line, when a transient analysis is desired starting from other than the quiescent operating point. See the .ic control line for a better way to set initial conditions.
BSIM2 model (level 5)
This model contains many improvements over BSIM1 and is suitable for analog simulation. Nevertheless, even BSIM2 breaks transistor operation into several distinct regions and this leads to discontinuities in the first derivative in CV and IV characteristics that can cause numerical problems during simulation.
BSIM3 model (levels 8, 49)
BSIM3 solves the numerical problems of previous models with the introduction of smoothing functions. It adopts a single equation to describe device characteristics in the operating regions. This approach eliminates the discontinuities in the IV and CV characteristics. The original model, BSIM3 evolved through three versions: BSIM3v1, BSIM3v2 and BSIM3v3. Both BSIM3v1 and BSIM3v2 had suffered from many mathematical problems and were replaced by BSIM3v3. The latter is the only surviving release and has itself a long revision history.
The following table summarizes the story of this model:
Release

Date

Notes

Version flag

BSIM3v3.0

10/30/1995

3.0


BSIM3v3.1

12/09/1996

3.1


BSIM3v3.2

06/16/1998

Revisions available: BSIM3v3.2.2, BSIM3v3.2.3, and BSIM3v3.2.4
Parallel processing with OpenMP is available for BSIM3v3.2.4.

3.2, 3.2.2, 3.2.3, 3.2.4

BSIM3v3.3

07/29/2005

Parallel processing with OpenMP is available for this model.

3.3.0

BSIM3v2 and 3v3 models has proved for accurate use in 0.18 (\mu m) technologies. The model is publicly available as source code form from University of California, Berkeley.
A detailed description is given in the user's manual available from here .
We recommend that you use only the most recent BSIM3 models (version 3.3.0), because it contains corrections to all known bugs. To achieve that, change the version parameter in your modelcard files to
VERSION = 3.3.0.
If no version number is given in the .model card, this (newest) version is selected as the default.
BSIM3v3.2.4 supports the extra model parameter lmlt on channel length scaling and is still used by many foundries today.
The older models will not be supported, they are made available for reference only.
BSIM4 model (levels 14, 54)
This is the newest class of the BSIM family and introduces noise modeling and extrinsic parasitics. BSIM4, as the extension of BSIM3 model, addresses the MOSFET physical effects into sub100nm regime. It is a physicsbased, accurate, scalable, robust and predictive MOSFET SPICE model for circuit simulation and CMOS technology development. It is developed by the BSIM Research Group in the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley (see BSIM4 home page). BSIM4 has a long revision history, which is summarized below.
Release

Date

Notes

Version flag

BSIM4.0.0

03/24/2000


BSIM4.1.0

10/11/2000


BSIM4.2.0

04/06/2001


BSIM4.2.1

10/05/2001

*

4.2.1

BSIM4.3.0

05/09/2003

*

4.3.0

BSIM4.4.0

03/04/2004

*

4.4.0

BSIM4.5.0

07/29/2005

* **

4.5.0

BSIM4.6.0

12/13/2006


...


BSIM4.6.5

09/09/2009

* **

4.6.5

BSIM4.7.0

04/08/2011

* **

4.7

BSIM4.8.1

15/02/2017

* **

4.8

*) supported in ngspice, using e.g. the version=<version flag> flag in the parameter file.
**) Parallel processing using OpenMP support is available for this model.
Details of any revision are to be found in the Berkeley user's manuals, a pdf download of the most recent edition is to be found here.
We recommend that you use only the most recent BSIM4 model (version 4.8.1), because it contains corrections to all known bugs. To achieve that, change the version parameter in your modelcard files to
VERSION = 4.8.
If no version number is given in the .model card, this (newest) version is selected as the default. The older models will typically not be supported, they are made available for reference only.
EKV model
Level 44 model (EKV) is not available in the standard distribution since it is not released in source form by the EKV group. To obtain the code please refer to the (EKV model home page, EKV group home page). A verilogA version is available contributed by Ivan Riis Nielsen 11/2006.
BSIMSOI models (levels 10, 58, 55, 56, 57)
BSIMSOI is a SPICE compact model for SOI (SiliconOnInsulator) circuit design, created by University of California at Berkeley. This model is formulated on top of the BSIM3 framework. It shares the same basic equations with the bulk model so that the physical nature and smoothness of BSIM3v3 are retained. Four models are supported in ngspice, those based on BSIM3 and modeling fully depleted (FD, level 55), partially depleted (PD, level 57) and both (DD, level 56), as well as the modern BSIMSOI version 4 model (levels 10, 58). Detailed descriptions are beyond the scope of this manual, but see e.g. BSIMSOIv4.4 User Manual for a very extensive description of the recent model version. OpenMP support is available for levels 10, 58, version 4.4.
SOI3 model (level 60)
see literature citation [18] for a description.
HiSIM models of the University of Hiroshima
There are two model implementations available  see also HiSIM Research Center:
 HiSIM2 model: SurfacePotentialBased MOSFET Model for Circuit Simulation version 2.8.0  level 68 (see link to HiSIM2 for source code and manual).
 HiSIM_HV model: SurfacePotentialBased HV/LDMOSFET Model for Circuit Simulation version 1.2.4 and 2.2.0  level 73 (see link to HiSIM_HV for source code and manual).
Power MOSFET model (VDMOS)
The VDMOS model is a relativly simple power MOS model with 3 terminals drain, gate, and source. Its current equations are based on the MOS1 model. The gatesource capacitance is set to a constant value by parameter Cgs. The drainsource capacitance is evaluated from parameters Cgdmax, Cgdmin, and A. The drainsource capacitance is that of a parallel pn diode and calculated by Cjo, fc, and m. Leakage and breakdown are modelled by the parallel pn diodes as well, using is and other parameters. A subthreshold current model is available, using a single parameter ksubthres. Quasisaturation is modelled with parameters rq and vq. Mtriode may be used here as well.
This model does not have a level parameter. It is invoked by the VDMOS token preceeding the parameters on the .model line. Pchannel or nchannel are selected by the flags Pchan and Nchan. If no flag is given, nchannel is the default. Standard MOS instance parameters W and L are not aknowledged because they are no design parameters and are not provided by the device manufacturers.
Please note that the device multiplier for this model is named mu!
The following 'parameters' in the .model line are no model parameters, but serve information purposes for the user: mfg=..., Vds=..., Ron=..., and Qg=... They are ignored by ngspice.
General form:
MXXXXXXX nd ng ns mname <mu=val> <temp=t> <dtemp=t>
Example:
M1 24 2 0 IXTH48P20P
.MODEL IXTH48P20P VDMOS Pchan Vds=200 VTO=4 KP=10 Lambda=5m
+ Mtriode=0.3 Ksubthres=120m Rs=10m Rd=20m Rds=200e6
+ Cgdmax=6000p Cgdmin=100p A=0.25 Cgs=5000p Cjo=9000p
+ Is=2e6 Rb=20m BV=200 IBV=250e6 NBV=4 TT=260e9
NGSPICE VDMOS parameters
Name

Parameter

Units

Default

Example


NCHAN

NMOS



default, if not given



PCHAN

PMOS

required, if PMOS




VTO

Zerobias threshold voltage (V_{T0})

V

0.0


KP

Transconductance parameter

$\frac{A}{V^{2}}$

1.0


LAMBDA

Channel length modulation (λ)

$\frac{1}{V}$

0.0


THETA

Vgs influence on mobility

$\frac{1}{V}$

0.0


RD

Drain ohmic resistance

Ω

0.0


RS

Source ohmic resistance

Ω

0.0


RG

Gate ohmic resistance

Ω

0.0


KF

Flicker noise coefficient



0.0


AF

Flicker noise exponent



1.0


TNOM

Parameter measurement temperature

C

27


RQ

Quasi saturation resistance fitting parameter

Ω

0.0


VQ

Quasi saturation voltage fitting parameter

V

1.0e14


MTRIODE

Conductance multiplier in triode region

−

1.0


SUBSLOPE

slope in the dual parameter subthreshold model



0.0


SUBSHIFT

shift along gate voltage axis in the dual parameter subthreshold model

V

0.0


KSUBTHRES

slope in the single parameter subthreshold model



0.0


BV

Vds breakdown voltage

V

∞


IBV

Current at Vds=bv

A

1.0e10


NBV

Vds breakdown emission coefficient



1.0


RDS

Drainsource shunt resistance

Ω

∞


RB

Body diode ohmic resistance

Ω

0.0


N

Body diode emission coefficient



0.0


TT

Body diode transit time

s

0.0


EG

Body diode activation energy for temperature effect on IS

eV

1.11


XTI

Body diode saturation current temperature exponent




IS

Body diode saturation current

A

1e14


VJ

Body diode junction potential

V

0.8


FC

Body diode coefficient for forwardbias depletion capacitance formula



0.0


CJO

Zerobias body diode junction capacitance

F

0.0


M

Body diode grading coefficient



1.0


CGDMIN

Minimum nonlinear GD capacitance

F

0.0


CGDMAX

Maximum nonlinear GD capacitance

F

0.0


A

Nonlinear Cgd capacitance parameter



1


CGS

Gatesource capacitance

F

0.0

MixedMode and Behavioral Modeling with XSPICE
Ngspice implements XSPICE extensions for behavioral and mixedmode (analog and digital) modeling. In the XSPICE framework this is referred to as code level modeling. Behavioral modeling may benefit dramatically because XSPICE offers a means to add analog functionality programmed in C. Many examples (amplifiers, oscillators, filters ...) are presented in the following. Even more flexibility is available because you may define your own models and use them in addition and in combination with all the already existing ngspice functionality. Digital and mixed mode simulation is speeded up significantly by simulating the digital part in an event driven manner, in that state equations use only a few allowed states and are evaluated only during switching, and not continuously in time and signal as in a pure analog simulator.
This chapter describes the predefined models available in ngspice, stemming from the original XSPICE simulator or being added to enhance the usability. The instructions for writing new code models are given in Chapt. 28.
To make use of the XSPICE extensions, you need to compile them in. Linux, CYGWIN, MINGW and other users may add the flag enablexspice to their ./configure command and then recompile. The prebuilt ngspice for Windows distribution has XSPICE already enabled. For detailed compiling instructions see Chapt. 32.1.
Code Model Element & .MODEL Cards
Syntax
Ngspice includes a library of predefined `Code Models' that can be placed within any circuit description in a manner similar to that used to place standard device models. Code model instance cards always begin with the letter `A', and always make use of a .MODEL card to describe the code model desired. Section 28 of this document goes into greater detail as to how a code model similar to the predefined models may be developed, but once any model is created and linked into the simulator it may be placed using one instance card and one .MODEL card (note here we conform to the SPICE custom of referring to a single logical line of information as a `card'). As an example, the following uses a predefined `gain' code model taking as an input some value on node 1, multiplies it by a gain of 5.0, and outputs the new value to node 2. Note that, by convention, input ports are specified first on code models. Output ports follow the inputs.
Example:
a1 1 2 amp
.model amp gain(gain=5.0)
In this example the numerical values picked up from singleended (i.e. ground referenced) input node 1 and output to singleended output node 2 will be voltages, since in the Interface Specification File for this code model (i.e., gain), the default port type is specified as a voltage (more on this later). However, if you didn't know this, the following modifications to the instance card could be used to insure it:
Example:
a1 %v(1) %v(2) amp
.model amp gain(gain=5.0)
The specification %v preceding the input and output node numbers of the instance card indicate to the simulator that the inputs to the model should be singleended voltage values. Other possibilities exist, as described later.
Some of the other features of the instance and .MODEL cards are worth noting. Of particular interest is the portion of the .MODEL card that specifies gain=5.0. This portion of the card assigns a value to a parameter of the `gain' model. There are other parameters that can be assigned values for this model, and in general code models will have several. In addition to numeric values, code model parameters can take nonnumeric values (such as TRUE and FALSE), and even vector values. All of these topics will be discussed at length in the following pages. In general, however, the instance and .MODEL cards that define a code model will follow the abstract form described below. This form illustrates that the number of inputs and outputs and the number of parameters that can be specified is relatively openended and can be interpreted in a variety of ways (note that anglebrackets `<' and `>' enclose optional inputs):
Example:
AXXXXXXX <%v,%i,%vd,%id,%g,%gd,%h,%hd, or %d>
+ <[> <~><%v,%i,%vd,%id,%g,%gd,%h,%hd, or %d>
+ <NIN1 or +NIN1 NIN1 or "null">
+ <~>...<NIN2.. <]> >
+ <%v,%i,%vd,%id,%g,%gd,%h,%hd,%d or %vnam>
+ <[> <~><%v,%i,%vd,%id,%g,%gd,%h,%hd,
or %d><NOUT1 or +NOUT1 NOUT1>
+ <~>...<NOUT2.. <]>>
+ MODELNAME
.MODEL MODELNAME MODELTYPE
+ <( PARAMNAME1= <[> VAL1 <VAL2... <]>> PARAMNAME2..>)>
Square brackets ([ ]) are used to enclose vector input nodes. In addition, these brackets are used to delineate vectors of parameters.
The literal string `null', when included in a node list, is interpreted as no connection at that input to the model. `Null' is not allowed as the name of a model's input or output if the model only has one input or one output. Also, `null' should only be used to indicate a missing connection for a code model; use on other XSPICE component is not interpreted as a missing connection, but will be interpreted as an actual node name.
The tilde, `~', when prepended to a digital node name, specifies that the logical value of that node be inverted prior to being passed to the code model. This allows for simple inversion of input and output polarities of a digital model in order to handle logically equivalent cases and others that frequently arise in digital system design. The following example defines a NAND gate, one input of which is inverted:
a1 [~1 2] 3 nand1
.model nand1 d_nand (rise_delay=0.1 fall_delay=0.2)
The optional symbols %v, %i, %vd, etc. specify the type of port the simulator is to expect for the subsequent port or port vector. The meaning of each symbol is given in Table 12.1.
Port Type Modifiers
Modifier
Interpretation
%v
represents a singleended voltage port  one node name or number is expected for each port.
%i
represents a singleended current port  one node name or number is expected for each port.
%g
represents a singleended voltageinput, currentoutput (VCCS) port  one node name or number is expected for each port. This type of port is automatically an input/output.
%h
represents a singleended currentinput, voltageoutput (CCVS) port  one node name or number is expected for each port. This type of port is automatically an input/output.
%d
represents a digital port  one node name or number is expected for each port. This type of port may be either an input or an output.
%vnam
represents the name of a voltage source, the current through which is taken as an input. This notation is provided primarily in order to allow models defined using SPICE2G6 syntax to operate properly in XSPICE.
%vd
represents a differential voltage port  two node names or numbers are expected for each port.
%id
represents a differential current port  two node names or numbers are expected for each port.
%gd
represents a differential VCCS port  two node names or numbers are expected for each port.
%hd
represents a differential CCVS port  two node names or numbers are expected for each port.
Table 12.1: Port Type Modifiers
The symbols described in Table 12.1 may be omitted if the default port type for the model is desired. Note that nondefault port types for multiinput or multioutput (vector) ports must be specified by placing one of the symbols in front of EACH vector port. On the other hand, if all ports of a vector port are to be declared as having the same nondefault type, then a symbol may be specified immediately prior to the opening bracket of the vector. The following examples should make this clear:
Example 1:  Specifies two differential voltage connections, one
to nodes 1 & 2, and one to nodes 3 & 4.
%vd [1 2 3 4]
Example 2:  Specifies two singleended connections to node 1 and
at node 2, and one differential connection to
nodes 3 & 4.
%v [1 2 %vd 3 4]
Example 3:  Identical to the previous example...parenthesis
are added for additional clarity.
%v [1 2 %vd(3 4)]
Example 4:  Specifies that the node numbers are to be treated in the
default fashion for the particular model.
If this model had `%v'' as a default for this
port, then this notation would represent four singleended
voltage connections.
[1 2 3 4]
The parameter names listed on the .MODEL card must be identical to those named in the code model itself. The parameters for each predefined code model are described in detail in Sections 12.2 (analog), 12.3 (Hybrid, A/D) and 12.4 (digital). The steps required in order to specify parameters for userdefined models are described in Chapter 28.
Examples
The following is a list of instance card and associated .MODEL card examples showing use of predefined models within an XSPICE deck:
a1 1 2 amp
.model amp gain(in_offset=0.1 gain=5.0 out_offset=0.01)
a2 %i[1 2] 3 sum1
.model sum1 summer(in_offset=[0.1 0.2] in_gain=[2.0 1.0]
+ out_gain=5.0 out_offset=0.01)
a21 %i[1 %vd(2 5) 7 10] 3 sum2
.model sum2 summer(out_gain=10.0)
a5 1 2 limit5
.model limit5 limit(in_offset=0.1 gain=2.5
+ out_lower_limit=5.0 out_upper_limit=5.0 limit_range=0.10
+ fraction=FALSE)
a7 2 %id(4 7) xfer_cntl1
.model xfer_cntl1 pwl(x_array=[2.0 1.0 2.0 4.0 5.0]
+ y_array=[0.2 0.2 0.1 2.0 10.0]
+ input_domain=0.05 fraction=TRUE)
a8 3 %gd(6 7) switch3
.model switch3 aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e6
+ r_on=10.0 log=TRUE)
Search path for file input
Several code models (filesource 12.2.8, d_source 12.4.21, d_state 12.4.18) call additional files for supply of input data. A call to file="path/filename" (or input_file=, state_file=) in the .model card will start a search sequence for finding the file. path may be an absolute path. If path is omitted or is a relative path, filename is looked for according to the following search list:
 Infile_Path/<path/filename> (Infile_Path is the path of the input file *.sp containing the netlist)
 NGSPICE_INPUT_DIR/<path/filename> (where an additional path is set by the environmental variable)
 <path/filename> (where the search is relative to the current directory (OS dependent))
Analog Models
The following analog models are supplied with XSPICE. The descriptions included consist of the model Interface Specification File and a description of the model's operation. This is followed by an example of a simulatordeck placement of the model, including the .MODEL card and the specification of all available parameters.
Gain
NAME_TABLE:
C_Function_Name: cm_gain
Spice_Model_Name: gain
Description: "A simple gain block"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id]
Vector: no no
Vector.Bounds:  
Null.Allowed: no no
PARAMETER_TABLE:
Parameter_Name: in_offset gain out_offset
Description: "input offset" "gain" "output offset"
Data_Type: real real real
Default_Value: 0.0 1.0 0.0
Limits:   
Vector: no no no
Vector_Bounds:   
Null_Allowed: yes yes yes
 Description:
This function is a simple gain block with optional offsets on the input and the output. The input offset is added to the input, the sum is then multiplied by the gain, and the result is produced by adding the output offset. This model will operate in DC, AC, and Transient analysis modes.
Example:
a1 1 2 amp
.model amp gain(in_offset=0.1 gain=5.0
+ out_offset=0.01)
Summer
NAME_TABLE:
C_Function_Name: cm_summer
Spice_Model_Name: summer
Description: "A summer block"
PORT_TABLE:
Port Name: in out
Description: "input vector" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id]
Vector: yes no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: in_offset in_gain
Description: "input offset vector" "input gain vector"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: yes yes
Vector_Bounds: in in
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: out_gain out_offset
Description: "output gain" "output offset"
Data_Type: real real
Default_Value: 1.0 0.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
 Description:
This function is a summer block with 2toN input ports. Individual gains and offsets can be applied to each input and to the output. Each input is added to its respective offset and then multiplied by its gain. The results are then summed, multiplied by the output gain and added to the output offset. This model will operate in DC, AC, and Transient analysis modes.
Example usage:
a2 [1 2] 3 sum1
.model sum1 summer(in_offset=[0.1 0.2] in_gain=[2.0 1.0]
+ out_gain=5.0 out_offset=0.01)
Multiplier
NAME_TABLE:
C_Function_Name: cm_mult
Spice_Model_Name: mult
Description: "multiplier block"
PORT_TABLE:
Port_Name: in out
Description: "input vector" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id]
Vector: yes no
Vector_Bounds: [2 ] 
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: in_offset in_gain
Description: "input offset vector" "input gain vector"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: yes yes
Vector_Bounds: in in
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: out_gain out_offset
Description: "output gain" "output offset"
Data_Type: real real
Default_Value: 1.0 0.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
 Description:
This function is a multiplier block with 2toN input ports. Individual gains and offsets can be applied to each input and to the output. Each input is added to its respective offset and then multiplied by its gain. The results are multiplied along with the output gain and are added to the output offset. This model will operate in DC, AC, and Transient analysis modes. However, in ac analysis it is important to remember that results are invalid unless only one input of the multiplier is connected to a node that i connected to an AC signal (this is exemplified by the use of a multiplier to perform a potentiometer function: one input is DC, the other carries the AC signal).
Example SPICE Usage:
a3 [1 2 3] 4 sigmult
.model sigmult mult(in_offset=[0.1 0.1 0.1]
+ in_gain=[10.0 10.0 10.0] out_gain=5.0 out_offset=0.05)
Divider
NAME_TABLE:
C_Function_Name: cm_divide
Spice_Model_Name: divide
Description: "divider block"
PORT_TABLE:
Port_Name: num den out
Description: "numerator" "denominator" "output"
Direction: in in out
Default_Type: v v v
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam] [v,vd,i,id]
Vector: no no no
Vector_Bounds:   
Null_Allowed: no no no
PARAMETER_TABLE:
Parameter_Name: num_offset num_gain
Description: "numerator offset" "numerator gain"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: den_offset den_gain
Description: "denominator offset" "denominator gain"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: den_lower_limit
Description: "denominator lower limit"
Data_Type: real
Default_Value: 1.0e10
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: den_domain
Description: "denominator smoothing domain"
Data_Type: real
Default_Value: 1.0e10
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: fraction
Description: "smoothing fraction/absolute value switch"
Data_Type: boolean
Default_Value: false
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: out_gain out_offset
Description: "output gain" "output offset"
Data_Type: real real
Default_Value: 1.0 0.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
 Description:
This function is a twoquadrant divider. It takes two inputs; num (numerator) and den (denominator). Divide offsets its inputs, multiplies them by their respective gains, divides the results, multiplies the quotient by the output gain, and offsets the result. The denominator is limited to a value above zero via a user specified lower limit. This limit is approached through a quadratic smoothing function, the domain of which may be specified as a fraction of the lower limit value (default), or as an absolute value. This model will operate in DC, AC and Transient analysis modes. However, in ac analysis it is important to remember that results are invalid unless only one input of the divider is connected to a node that is connected to an ac signal (this is exemplified by the use of the divider to perform a potentiometer function: one input is dc, the other carries the ac signal).
Example SPICE Usage:
a4 1 2 4 divider
.model divider divide(num_offset=0.1 num_gain=2.5 den_offset=0.1
+ den_gain=5.0 den_lower_limit=1e5 den_domain=1e6
+ fraction=FALSE out_gain=1.0 out_offset=0.0)
Limiter
NAME_TABLE:
C_Function_Name: cm_limit
Spice_Model_Name: limit
Description: "limit block"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: in_offset gain
Description: "input offset" "gain"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: out_lower_limit out_upper_limit
Description: "output lower limit" "output upper limit"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: limit_range
Description: "upper & lower smoothing range"
Data_Type: real
Default_Value: 1.0e6
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: fraction
Description: "smoothing fraction/absolute value switch"
Data_Type: boolean
Default_Value: FALSE
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The Limiter is a single input, single output function similar to the Gain Block. However, the output of the Limiter function is restricted to the range specified by the output lower and upper limits. This model will operate in DC, AC and Transient analysis modes. Note that the limit range is the value below the upper limit and above the lower limit at which smoothing of the output begins. For this model, then, the limit range represents the delta with respect to the output level at which smoothing occurs. Thus, for an input gain of 2.0 and output limits of 1.0 and 1.0 volts, the output will begin to smooth out at (\pm)0.9 volts, which occurs when the input value is at (\pm)0.4.
Example SPICE Usage:
a5 1 2 limit5
.model limit5 limit(in_offset=0.1 gain=2.5 out_lower_limit=5.0
+ out_upper_limit=5.0 limit_range=0.10 fraction=FALSE)
Controlled Limiter
NAME_TABLE:
C_Function_Name: cm_climit
Spice_Model_Name: climit
Description: "controlled limiter block"
PORT_TABLE:
Port_Name: in cntl_upper
Description: "input" "upper lim. control input"
Direction: in in
Default_Type: v v
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PORT_TABLE:
Port_Name: cntl_lower out
Description: "lower limit control input" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: in_offset gain
Description: "input offset" "gain"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: upper_delta lower_delta
Description: "output upper delta" "output lower delta"
Data_Type: real real
Default_Value: 0.0 0.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: limit_range fraction
Description: "upper & lower sm. range" "smoothing %/abs switch"
Data_Type: real boolean
Default_Value: 1.0e6 FALSE
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
 Description:
The Controlled Limiter is a single input, single output function similar to the Gain Block. However, the output of the Limiter function is restricted to the range specified by the output lower and upper limits. This model will operate in DC, AC, and Transient analysis modes. Note that the limit range is the value below the (cntlupper) limit and above the (cntllower) limit at which smoothing of the output begins (minimum positive value of voltage must exist between the (cntlupper) input and the (cntllower) input at all times). For this model, then, the limit range represents the delta with respect to the output level at which smoothing occurs. Thus, for an input gain of 2.0 and output limits of 1.0 and 1.0 volts, the output will begin to smooth out at (\pm)0.9 volts, which occurs when the input value is at (\pm)0.4. Note also that the Controlled Limiter code tests the input values of (cntlupper) and (cntllower) to make sure that they are spaced far enough apart to guarantee the existence of a linear range between them. The range is calculated as the difference between ((cntlupper  upperdelta  limitrange)) and ((cntllower + lowerdelta + limitrange)) and must be greater than or equal to zero. Note that when the limit range is specified as a fractional value, the limit range used in the above is taken as the calculated fraction of the difference between (cntlupper) and (cntllower). Still, the potential exists for too great a limit range value to be specified for proper operation, in which case the model will return an error message.
Example SPICE Usage:
a6 3 6 8 4 varlimit
.
.
.model varlimit climit(in_offset=0.1 gain=2.5 upper_delta=0.0
+ lower_delta=0.0 limit_range=0.10 fraction=FALSE)
PWL Controlled Source
NAME_TABLE:
C_Function_Name: cm_pwl
Spice_Model_Name: pwl
Description: "piecewise linear controlled source"
PORT_TABLE:
Port_Name: in out
Description: "input" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: x_array y_array
Description: "xelement array" "yelement array"
Data_Type: real real
Default_Value:  
Limits:  
Vector: yes yes
Vector_Bounds: [2 ] [2 ]
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: input_domain fraction
Description: "input sm. domain" "smoothing %/abs switch"
Data_Type: real boolean
Default_Value: 0.01 TRUE
Limits: [1e12 0.5] 
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
STATIC_VAR_TABLE:
Static_Var_Name: last_x_value
Data_Type: pointer
Description: "iteration holding variable for limiting"
 Description:
The PieceWise Linear Controlled Source is a single input, single output function similar to the Gain Block. However, the output of the PWL Source is not necessarily linear for all values of input. Instead, it follows an I/O relationship specified by you via the x_array and y_array coordinates. This is detailed below.
The x_array and y_array values represent vectors of coordinate points on the x and y axes, respectively. The x_array values are progressively increasing input coordinate points, and the associated y_array values represent the outputs at those points. There may be as few as two (x_array[n], y_array[n]) pairs specified, or as many as memory and simulation speed allow. This permits you to very finely approximate a nonlinear function by capturing multiple inputoutput coordinate points.
Two aspects of the PWL Controlled Source warrant special attention. These are the handling of endpoints and the smoothing of the described transfer function near coordinate points.
In order to fully specify outputs for values of in outside of the bounds of the PWL function (i.e., less than x_array[0] or greater than x_array[n], where n is the largest userspecified coordinate index), the PWL Controlled Source model extends the slope found between the lowest two coordinate pairs and the highest two coordinate pairs. This has the effect of making the transfer function completely linear for in less than x_array[0] and in greater than x_array[n]. It also has the potentially subtle effect of unrealistically causing an output to reach a very large or small value for large inputs. You should thus keep in mind that the PWL Source does not inherently provide a limiting capability.
In order to diminish the potential for nonconvergence of simulations when using the PWL block, a form of smoothing around the x_array, y_array coordinate points is necessary. This is due to the iterative nature of the simulator and its reliance on smooth first derivatives of transfer functions in order to arrive at a matrix solution. Consequently, the input_domain and fraction parameters are included to allow you some control over the amount and nature of the smoothing performed.
Fraction is a switch that is either TRUE or FALSE. When TRUE (the default setting), the simulator assumes that the specified input domain value is to be interpreted as a fractional figure. Otherwise, it is interpreted as an absolute value. Thus, if fraction=TRUE and input_domain=0.10, The simulator assumes that the smoothing radius about each coordinate point is to be set equal to 10% of the length of either the x_array segment above each coordinate point, or the x_array segment below each coordinate point. The specific segment length chosen will be the smallest of these two for each coordinate point.
On the other hand, if fraction=FALSE and input=0.10, then the simulator will begin smoothing the transfer function at 0.10 volts (or amperes) below each x_array coordinate and will continue the smoothing process for another 0.10 volts (or amperes) above each x_array coordinate point. Since the overlap of smoothing domains is not allowed, checking is done by the model to ensure that the specified input domain value is not excessive.
One subtle consequence of the use of the fraction=TRUE feature of the PWL Controlled Source is that, in certain cases, you may inadvertently create extreme smoothing of functions by choosing inappropriate coordinate value points. This can be demonstrated by considering a function described by three coordinate pairs, such as (1,1), (1,1), and (2,1). In this case, with a 10% input_domain value specified (fraction=TRUE, input_domain=0.10), you would expect to see rounding occur between in=0.9 and in=1.1, and nowhere else. On the other hand, if you were to specify the same function using the coordinate pairs (100,100), (1,1) and (201,1), you would find that rounding occurs between in=19 and in=21. Clearly in the latter case the smoothing might cause an excessive divergence from the intended linearity above and below in=1.
Example SPICE Usage:
a7 2 4 xfer_cntl1
.
.
.model xfer_cntl1 pwl(x_array=[2.0 1.0 2.0 4.0 5.0]
+ y_array=[0.2 0.2 0.1 2.0 10.0]
+ input_domain=0.05 fraction=TRUE)
Filesource
NAME_TABLE:
C_Function_Name: cm_filesource
Spice_Model_Name: filesource
Description: "File Source"
PORT_TABLE:
Port_Name: out
Description: "output"
Direction: out
Default_Type: v
Allowed_Types: [v,vd,i,id]
Vector: yes
Vector_Bounds: [1 ]
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: timeoffset timescale
Description: "time offset" "timescale"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: timerelative amplstep
Description: "relative time" "step amplitude"
Data_Type: boolean boolean
Default_Value: FALSE FALSE
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: amploffset amplscale
Description: "ampl offset" "amplscale"
Data_Type: real real
Default_Value:  
Limits:  
Vector: yes yes
Vector_Bounds: [1 ] [1 ]
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: file
Description: "file name"
Data_Type: string
Default_Value: "filesource.txt"
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The File Source is similar to the PieceWise Linear Source, except that the waveform data is read from a file instead of being taken from parameter vectors. The file format is line oriented ASCII. `#' and `;' are comment characters; all characters from a comment character until the end of the line are ignored. Each line consists of two or more real values. The first value is the time; subsequent values correspond to the outputs. Values are separated by spaces. Time values are absolute and must be monotonically increasing, unless timerelative is set to TRUE, in which case the values specify the interval between two samples and must be positive. Waveforms may be scaled and shifted in the time dimension by setting timescale and timeoffset.
Amplitudes can also be scaled and shifted using amplscale and amploffset. Amplitudes are normally interpolated between two samples, unless amplstep is set to TRUE.  Note:
The file named by the parameter filename in file="filename" is sought after according to a search list described in12.1.3.
Example SPICE Usage:
a8 %vd([1 0 2 0]) filesrc
.
.
.model filesrc filesource (file="sine.m" amploffset=[0 0] amplscale=[1 1]
+ timeoffset=0 timescale=1
+ timerelative=false amplstep=false)
Example input file:
# name: sine.m
# two output ports
# column 1: time
# columns 2, 3: values
0 0 1
3.90625e09 0.02454122852291229 0.9996988186962042
7.8125e09 0.04906767432741801 0.9987954562051724
1.171875e08 0.07356456359966743 0.9972904566786902
...
multi_input_pwl block
NAME_TABLE:
C_Function_Name: cm_multi_input_pwl
Spice_Model_Name: multi_input_pwl
Description: "multi_input_pwl block"
PORT_TABLE:
Port_Name: in out
Description: "input array" "output"
Direction: in out
Default_Type: vd vd
Allowed_Types: [vd,id] [vd,id]
Vector: yes no
Vector_Bounds: [2 ] 
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: x y
Description: "x array" "y array"
Data_Type: real real
Default_Value: 0.0 0.0
Limits:  
Vector: yes yes
Vector_Bounds: [2 ] [2 ]
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: model
Description: "model type"
Data_Type: string
Default_Value: "and"
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
Multiinput gate voltage controlled voltage source that supports and or or gating. The x's and y's represent the piecewise linear variation of output (y) as a function of input (x). The type of gate is selectable by the parameter model. In case the model is and, the smallest input determines the output value (i.e. the and function). In case the model is or, the largest input determines the output value (i.e. the or function). The inverse of these functions (i.e. nand and nor) is constructed by complementing the y array.
Example SPICE Usage:
a82 [1 0 2 0 3 0] 7 0 pwlm
.
.
.model pwlm multi_input_pwl((x=[2.0 1.0 2.0 4.0 5.0]
+ y=[0.2 0.2 0.1 2.0 10.0]
+ model="and")
Analog Switch
NAME_TABLE:
C_Function_Name: cm_aswitch
Spice_Model_Name: aswitch
Description: "analog switch"
PORT_TABLE:
Port Name: cntl_in out
Description: "input" "resistive output"
Direction: in out
Default_Type: v gd
Allowed_Types: [v,vd,i,id] [gd]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: cntl_off cntl_on
Description: "control `off' value" "control `on' value"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: r_off log
Description: "off resistance" "log/linear switch"
Data_Type: real boolean
Default_Value: 1.0e12 TRUE
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: r_on
Description: "on resistance"
Data_Type: real
Default_Value: 1.0
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The Analog Switch is a resistor that varies either logarithmically or linearly between specified values of a controlling input voltage or current. Note that the input is not internally limited. Therefore, if the controlling signal exceeds the specified OFF state or ON state value, the resistance may become excessively large or excessively small (in the case of logarithmic dependence), or may become negative (in the case of linear dependence). For the experienced user, these excursions may prove valuable for modeling certain devices, but in most cases you are advised to add limiting of the controlling input if the possibility of excessive control value variation exists.
Example SPICE Usage:
a8 3 %gd(6 7) switch3
.
.
.model switch3 aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e6
+ r_on=10.0 log=TRUE)
Zener Diode
NAME_TABLE:
C_Function_Name: cm_zener
Spice_Model_Name: zener
Description: "zener diode"
PORT_TABLE:
Port Name: z
Description: "zener"
Direction: inout
Default_Type: gd
Allowed_Types: [gd]
Vector: no
Vector_Bounds: 
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: v_breakdown i_breakdown
Description: "breakdown voltage" "breakdown current"
Data_Type: real real
Default_Value:  2.0e2
Limits: [1.0e6 1.0e6] [1.0e9 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: no yes
PARAMETER_TABLE:
Parameter_Name: i_sat n_forward
Description: "saturation current" "forward emission coefficient"
Data_Type: real real
Default_Value: 1.0e12 1.0
Limits: [1.0e15 ] [0.1 10]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: limit_switch
Description: "switch for onboard limiting (convergence aid)"
Data_Type: boolean
Default_Value: FALSE
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
STATIC_VAR_TABLE:
Static_Var_Name: previous_voltage
Data_Type: pointer
Description: "iteration holding variable for limiting"
 Description:
The Zener Diode models the DC characteristics of most zeners. This model differs from the Diode/Rectifier by providing a userdefined dynamic resistance in the reverse breakdown region. The forward characteristic is defined by only a single point, since most data sheets for zener diodes do not give detailed characteristics in the forward region.
The first three parameters define the DC characteristics of the zener in the breakdown region and are usually explicitly given on the data sheet.
The saturation current refers to the relatively constant reverse current that is produced when the voltage across the zener is negative, but breakdown has not been reached. The reverse leakage current determines the slight increase in reverse current as the voltage across the zener becomes more negative. It is modeled as a resistance parallel to the zener with value v breakdown / i rev.
Note that the limit switch parameter engages an internal limiting function for the zener. This can, in some cases, prevent the simulator from converging to an unrealistic solution if the voltage across or current into the device is excessive. If use of this feature fails to yield acceptable results, the convlimit option should be tried (add the following statement to the SPICE input deck: .options convlimit)
Example SPICE Usage:
a9 3 4 vref10
.
.
.model vref10 zener(v_breakdown=10.0 i_breakdown=0.02
+ r_breakdown=1.0 i_rev=1e6 i_sat=1e12)
Current Limiter
NAME_TABLE:
C_Function_Name: cm_ilimit
Spice_Model_Name: ilimit
Description: "current limiter block"
PORT_TABLE:
Port Name: in pos_pwr
Description: "input" "positive power supply"
Direction: in inout
Default_Type: v g
Allowed_Types: [v,vd] [g,gd]
Vector: no no
Vector_Bounds:  
Null_Allowed: no yes
PORT_TABLE:
Port Name: neg_pwr out
Description: "negative power supply" "output"
Direction: inout inout
Default_Type: g g
Allowed_Types: [g,gd] [g,gd]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes no
PARAMETER_TABLE:
Parameter_Name: in_offset gain
Description: "input offset" "gain"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: r_out_source r_out_sink
Description: "sourcing resistance" "sinking resistance"
Data_Type: real real
Default_Value: 1.0 1.0
Limits: [1.0e9 1.0e9] [1.0e9 1.0e9]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: i_limit_source
Description: "current sourcing limit"
Data_Type: real
Default_Value: 
Limits: [1.0e12 ]
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: i_limit_sink
Description: "current sinking limit"
Data_Type: real
Default_Value: 
Limits: [1.0e12 ]
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: v_pwr_range i_source_range
Description: "upper & lower power "sourcing current
supply smoothing range" smoothing range"
Data_Type: real real
Default_Value: 1.0e6 1.0e9
Limits: [1.0e15 ] [1.0e15 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: i_sink_range
Description: "sinking current smoothing range"
Data_Type: real
Default_Value: 1.0e9
Limits: [1.0e15 ]
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: r_out_domain
Description: "internal/external voltage delta smoothing range"
Data_Type: real
Default_Value: 1.0e9
Limits: [1.0e15 ]
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The Current Limiter models the behavior of an operational amplifier or comparator device at a high level of abstraction. All of its pins act as inputs; three of the four also act as outputs. The model takes as input a voltage value from the in connector. It then applies an offset and a gain, and derives from it an equivalent internal voltage (veq), which it limits to fall between pos_pwr and neg_pwr. If veq is greater than the output voltage seen on the out connector, a sourcing current will flow from the output pin. Conversely, if the voltage is less than vout, a sinking current will flow into the output pin.
Depending on the polarity of the current flow, either a sourcing or a sinking resistance value (r_out_source, r_out_sink) is applied to govern the vout/i_out relationship. The chosen resistance will continue to control the output current until it reaches a maximum value specified by either i_limit_source or i_limit_sink. The latter mimics the current limiting behavior of many operational amplifier output stages.
During all operation, the output current is reflected either in the pos_pwr connector current or the neg_pwr current, depending on the polarity of i_out. Thus, realistic power consumption as seen in the supply rails is included in the model.
The userspecified smoothing parameters relate to model operation as follows: v_pwr_range controls the voltage below vpos_pwr and above vneg_pwr inputs beyond which (veq = gain\left( {vin + v_{offset}} \right)) is smoothed; i_source_range specifies the current below i_limit_source at which smoothing begins, as well as specifying the current increment above i_out=0.0 at which i_pos_pwr begins to transition to zero; i_sink_range serves the same purpose with respect to i_limit_sink and i_neg_pwr that i_source_range serves for i_limit_source and i_pos_pwr; r_out_domain specifies the incremental value above and below (veqvout)=0.0 at which r_out will be set to r_out_source and r_out_sink, respectively. For values of (veqvout) less than r_out_domain and greater than r_out_domain, r_out is interpolated smoothly between r_out_source and r_out_sink.
Example SPICE Usage:
a10 3 10 20 4 amp3
.
.
.model amp3 ilimit(in_offset=0.0 gain=16.0 r_out_source=1.0
+ r_out_sink=1.0 i_limit_source=1e3
+ i_limit_sink=10e3 v_pwr_range=0.2
+ i_source_range=1e6 i_sink_range=1e6
+ r_out_domain=1e6)
Hysteresis Block
NAME_TABLE:
C_Function_Name: cm_hyst
Spice_Model_Name: hyst
Description: "hysteresis block"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: in_low in_high
Description: "input low value" "input high value"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: hyst out_lower_limit
Description: "hysteresis" "output lower limit"
Data_Type: real real
Default_Value: 0.1 0.0
Limits: [0.0 ] 
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: out_upper_limit input_domain
Description: "output upper limit" "input smoothing domain"
Data_Type: real real
Default_Value: 1.0 0.01
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: fraction
Description: "smoothing fraction/absolute value switch"
Data_Type: boolean
Default_Value: TRUE
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The Hysteresis block is a simple buffer stage that provides hysteresis of the output with respect to the input. The in low and in high parameter values specify the center voltage or current inputs about which the hysteresis effect operates. The output values are limited to out lower limit and out upper limit. The value of hyst is added to the in low and in high points in order to specify the points at which the slope of the hysteresis function would normally change abruptly as the input transitions from a low to a high value. Likewise, the value of hyst is subtracted from the in high and in low values in order to specify the points at which the slope of the hysteresis function would normally change abruptly as the input transitions from a high to a low value. In fact, the slope of the hysteresis function is never allowed to change abruptly but is smoothly varied whenever the input domain smoothing parameter is set greater than zero.
Example SPICE Usage:
a11 1 2 schmitt1
.
.
.model schmitt1 hyst(in_low=0.7 in_high=2.4 hyst=0.5
+ out_lower_limit=0.5 out_upper_limit=3.0
+ input_domain=0.01 fraction=TRUE)
Differentiator
NAME_TABLE:
C_Function_Name: cm_d_dt
Spice_Model_Name: d_dt
Description: "timederivative block"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: gain out_offset
Description: "gain" "output offset"
Data_Type: real real
Default_Value: 1.0 0.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: out_lower_limit out_upper_limit
Description: "output lower limit" "output upper limit"
Data_Type: real real
Default_Value:  
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: limit_range
Description: "upper & lower limit smoothing range"
Data_Type: real
Default_Value: 1.0e6
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The Differentiator block is a simple derivative stage that approximates the time derivative of an input signal by calculating the incremental slope of that signal since the previous time point. The block also includes gain and output offset parameters to allow for tailoring of the required signal, and output upper and lower limits to prevent convergence errors resulting from excessively large output values. The incremental value of output below the output upper limit and above the output lower limit at which smoothing begins is specified via the limit range parameter. In AC analysis, the value returned is equal to the radian frequency of analysis multiplied by the gain.
Note that since truncation error checking is not included in the d_dt block, it is not recommended that the model be used to provide an integration function through the use of a feedback loop. Such an arrangement could produce erroneous results. Instead, you should make use of the "integrate" model, which does include truncation error checking for enhanced accuracy.
Example SPICE Usage:
a12 7 12 slope_gen
.
.
.model slope_gen d_dt(out_offset=0.0 gain=1.0
+ out_lower_limit=1e12 out_upper_limit=1e12
+ limit_range=1e9)
Integrator
NAME_TABLE:
C_Function_Name: cm_int
Spice_Model_Name: int
Description: "timeintegration block"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: in_offset gain
Description: "input offset" "gain"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: out_lower_limit out_upper_limit
Description: "output lower limit" "output upper limit"
Data_Type: real real
Default_Value:  
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: limit_range
Description: "upper & lower limit smoothing range"
Data_Type: real
Default_Value: 1.0e6
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: out_ic
Description: "output initial condition"
Data_Type: real
Default_Value: 0.0
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The Integrator block is a simple integration stage that approximates the integral with respect to time of an input signal. The block also includes gain and input offset parameters to allow for tailoring of the required signal, and output upper and lower limits to prevent convergence errors resulting from excessively large output values. Note that these limits specify integrator behavior similar to that found in an operational amplifierbased integration stage, in that once a limit is reached, additional storage does not occur. Thus, the input of a negative value to an integrator that is currently driving at the out upper limit level will immediately cause a drop in the output, regardless of how long the integrator was previously summing positive inputs. The incremental value of output below the output upper limit and above the output lower limit at which smoothing begins is specified via the limit range parameter. In AC analysis, the value returned is equal to the gain divided by the radian frequency of analysis.
Note that truncation error checking is included in the int block. This should provide for a more accurate simulation of the time integration function, since the model will inherently request smaller time increments between simulation points if truncation errors would otherwise be excessive.
Example SPICE Usage:
a13 7 12 time_count
.
.
.model time_count int(in_offset=0.0 gain=1.0
+ out_lower_limit=1e12 out_upper_limit=1e12
+ limit_range=1e9 out_ic=0.0)
SDomain Transfer Function
NAME_TABLE:
C_Function_Name: cm_s_xfer
Spice_Model_Name: s_xfer
Description: "sdomain transfer function"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: in_offset gain
Description: "input offset" "gain"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: num_coeff
Description: "numerator polynomial coefficients"
Data_Type: real
Default_Value: 
Limits: 
Vector: yes
Vector_Bounds: [1 ]
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: den_coeff
Description: "denominator polynomial coefficients"
Data_Type: real
Default_Value: 
Limits: 
Vector: yes
Vector_Bounds: [1 ]
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: int_ic
Description: "integrator stage initial conditions"
Data_Type: real
Default_Value: 0.0
Limits: 
Vector: yes
Vector_Bounds: den_coeff
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: denormalized_freq
Description: "denorm. corner freq.(radians) for 1 rad/s coeffs"
Data_Type: real
Default_Value: 1.0
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The sdomain transfer function is a single input, single output transfer function in the Laplace transform variable `s' that allows for flexible modulation of the frequency domain characteristics of a signal. Ac and transient simulations are supported. The code model may be configured to produce an arbitrary sdomain transfer function with the following restrictions:
1. The degree of the numerator polynomial cannot exceed that
of the denominator polynomial in the variable "s".
2. The coefficients for a polynomial must be stated
explicitly. That is, if a coefficient is zero, it must be
included as an input to the num coeff or den coeff vector.
The order of the coefficient parameters is from that associated with the highestpowered term decreasing to that of the lowest. Thus, for the coefficient parameters specified below, the equation in `s' is shown:
.model filter s_xfer(gain=0.139713
+ num_coeff=[1.0 0.0 0.7464102]
+ den_coeff=[1.0 0.998942 0.001170077]
+ int_ic=[0 0])
It specifies a transfer function of the form
(N\left( s \right) = 0.139713 \cdot \frac{s^{2} + 0.7464102}{s^{2} + 0.998942s + 0.00117077})
The sdomain transfer function includes gain and in_offset (input offset) parameters to allow for tailoring of the required signal. There are no limits on the internal signal values or on the output value of the sdomain transfer function, so you are cautioned to specify gain and coefficient values that will not cause the model to produce excessively large values. In AC analysis, the value returned is equal to the real and imaginary components of the total sdomain transfer function at each frequency of interest.
The denormalized_freq term allows you to specify coefficients for a normalized filter (i.e. one in which the frequency of interest is 1 rad/s). Once these coefficients are included, specifying the denormalized frequency value `shifts' the corner frequency to the actual one of interest. As an example, the following transfer function describes a Chebyshev lowpass filter with a corner (passband) frequency of 1 rad/s:
(N\left( s \right) = 0.139713 \cdot \frac{1.0}{s^{2} + 1.09773s + 1.10251})
In order to define an s_xfer model for the above, but with the corner frequency equal to 1500 rad/s (9425 Hz), the following instance and model lines would be needed:
a12 node1 node2 cheby1
.model cheby1 s_xfer(num_coeff=[1] den_coeff=[1 1.09773 1.10251]
+ int_ic=[0 0] denormalized_freq=1500)
In the above, you add the normalized coefficients and scale the filter through the use of the denormalized freq parameter. Similar results could have been achieved by performing the denormalization prior to specification of the coefficients, and setting denormalized freq to the value 1.0 (or not specifying the frequency, as the default is 1.0 rad/s) Note in the above that frequencies are always specified as radians/second.
Truncation error checking is included in the sdomain transfer block. This should provide for more accurate simulations, since the model will inherently request smaller time increments between simulation points if truncation errors would otherwise be excessive.
The int_ic parameter is an array that must be of size one less as the array of values specified for the den_coeff parameter. Even if a 0 start value is required, you have to add the specific int_ic vector to the set of coefficients (see the examples above and below).
Example SPICE Usage:
a14 9 22 cheby_LP_3kHz
.
.
.model cheby_LP_3kHz s_xfer(in_offset=0.0 gain=1.0 int_ic=[0 0]
+ num_coeff=[1.0]
+ den_coeff=[1.0 1.42562 1.51620])
Slew Rate Block
NAME_TABLE:
C_Function_Name: cm_slew
Spice_Model_Name: slew
Description: "A simple slew rate follower block"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: rise_slope
Description: "maximum rising slope value"
Data_Type: real
Default_Value: 1.0e9
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: fall_slope
Description: "maximum falling slope value"
Data_Type: real
Default_Value: 1.0e9
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: range
Description: "smoothing range"
Data_Type: real
Default_Value: 0.1
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
This function is a simple slew rate block that limits the absolute slope of the output with respect to time to some maximum or value. The actual slew rate effects of overdriving an amplifier circuit can thus be accurately modeled by cascading the amplifier with this model. The units used to describe the maximum rising and falling slope values are expressed in volts or amperes per second. Thus a desired slew rate of 0.5 V/(\mu s) will be expressed as 0.5e+6, etc.
The slew rate block will continue to raise or lower its output until the difference between the input and the output values is zero. Thereafter, it will resume following the input signal, unless the slope again exceeds its rise or fall slope limits. The range input specifies a smoothing region above or below the input value. Whenever the model is slewing and the output comes to within the input + or  the range value, the partial derivative of the output with respect to the input will begin to smoothly transition from 0.0 to 1.0. When the model is no longer slewing (output = input), dout/din will equal 1.0.
Example SPICE Usage:
a15 1 2 slew1
.model slew1 slew(rise_slope=0.5e6 fall_slope=0.5e6)
Inductive Coupling
NAME_TABLE:
C_Function_Name: cm_lcouple
Spice_Model_Name: lcouple
Description: "inductive coupling (for use with 'core' model)"
PORT_TABLE:
Port_Name: l mmf_out
Description: "inductor" "mmf output (in ampereturns)"
Direction: inout inout
Default_Type: hd hd
Allowed_Types: [h,hd] [hd]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: num_turns
Description: "number of inductor turns"
Data_Type: real
Default_Value: 1.0
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
This function is a conceptual model that is used as a building block to create a wide variety of inductive and magnetic circuit models. This function is normally used in conjunction with the core model, but can also be used with resistors, hysteresis blocks, etc. to build up systems that mock the behavior of linear and nonlinear components.
The lcouple takes as an input (on the `l' port), a current. This current value is multiplied by the num_turns value, N, to produce an output value (a voltage value that appears on the mmf_out port). The mmf_out acts similar to a magnetomotive force in a magnetic circuit; when the lcouple is connected to the core model, or to some other resistive device, a current will flow. This current value (which is modulated by whatever the lcouple is connected to) is then used by the lcouple to calculate a voltage `seen' at the l port. The voltage is a function of the derivative with respect to time of the current value seen at mmf_out.
The most common use for lcouples will be as a building block in the construction of transformer models. To create a transformer with a single input and a single output, you would require two lcouple models plus one core model. The process of building up such a transformer is described under the description of the core model, below.
Example SPICE Usage:
a150 (7 0) (9 10) lcouple1
.model lcouple1 lcouple(num_turns=10.0)
Magnetic Core
NAME_TABLE:
C_Function_Name: cm_core
Spice_Model_Name: core
Description: "magnetic core"
PORT_TABLE:
Port_Name: mc
Description: "magnetic core"
Direction: inout
Default_Type: gd
Allowed_Types: [g,gd]
Vector: no
Vector_Bounds: 
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: H_array B_array
Description: "magnetic field array" "flux density array"
Data_Type: real real
Default_Value:  
Limits:  
Vector: yes yes
Vector_Bounds: [2 ] [2 ]
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: area length
Description: "crosssectional area" "core length"
Data_Type: real real
Default_Value:  
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: input_domain
Description: "input sm. domain"
Data_Type: real
Default_Value: 0.01
Limits: [1e12 0.5]
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: fraction
Description: "smoothing fraction/abs switch"
Data_Type: boolean
Default_Value: TRUE
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: mode
Description: "mode switch (1 = pwl, 2 = hyst)"
Data_Type: int
Default_Value: 1
Limits: [1 2]
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: in_low in_high
Description: "input low value" "input high value"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: hyst out_lower_limit
Description: "hysteresis" "output lower limit"
Data_Type: real real
Default_Value: 0.1 0.0
Limits: [0 ] 
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: out_upper_limit
Description: "output upper limit"
Data_Type: real
Default_Value: 1.0
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
This function is a conceptual model that is used as a building block to create a wide variety of inductive and magnetic circuit models. This function is almost always expected to be used in conjunction with the lcouple model to build up systems that mock the behavior of linear and nonlinear magnetic components. There are two fundamental modes of operation for the core model. These are the pwl mode (which is the default, and which is the most likely to be of use to you) and the hysteresis mode. These are detailed below.
PWL Mode (mode = 1)
The core model in PWL mode takes as input a voltage that it treats as a magnetomotive force (mmf) value. This value is divided by the total effective length of the core to produce a value for the Magnetic Field Intensity, H. This value of H is then used to find the corresponding Flux Density, B, using the piecewise linear relationship described by you in the H array / B array coordinate pairs. B is then multiplied by the crosssectional area of the core to find the Flux value, which is output as a current. The pertinent mathematical equations are listed below:
[H = \frac{mmf}{L},{ where} L = Length]
Here H, the Magnetic Field Intensity, is expressed in ampereturns/meter.
[B = f\left( H \right)]
The B value is derived from a piecewise linear transfer function described to the model via the (H_array[],B_array[]) parameter coordinate pairs. This transfer function does not include hysteretic effects; for that, you would need to substitute a HYST model for the core.
[\varphi = BA,{ where} A = Area]
The final current allowed to flow through the core is equal to (\varphi). This value in turn is used by the "lcouple" code model to obtain a value for the voltage reflected back across its terminals to the driving electrical circuit.
The following example code shows the use of two lcouple models and one core model to produce a simple primary/secondary transformer.
Example SPICE Usage:
a1 (2 0) (3 0) primary
.model primary lcouple (num_turns = 155)
a2 (3 4) iron_core
.model iron_core core (H_array = [1000 500 375 250 188 125 63 0
+ 63 125 188 250 375 500 1000]
+ B_array = [3.13e3 2.63e3 2.33e3 1.93e3
+ 1.5e3 6.25e4 2.5e4 0 2.5e4
+ 6.25e4 1.5e3 1.93e3 2.33e3
+ 2.63e3 3.13e3]
+ area = 0.01 length = 0.01)
a3 (5 0) (4 0) secondary
.model secondary lcouple (num_turns = 310)
HYSTERESIS Mode (mode = 2)
The core model in HYSTERESIS mode takes as input a voltage that it treats as a magnetomotive force (mmf) value. This value is used as input to the equivalent of a hysteresis code model block. The parameters defining the input low and high values, the output low and high values, and the amount of hysteresis are as in that model. The output from this mode, as in PWL mode, is a current value that is seen across the mc port. An example of the core model used in this fashion is shown below:
Example SPICE Usage:
a1 (2 0) (3 0) primary
.model primary lcouple (num_turns = 155)
a2 (3 4) iron_core
.model iron_core core (mode = 2 in_low=7.0 in_high=7.0
+ out_lower_limit=2.5e4 out_upper_limit=2.5e4
+ hyst = 2.3 )
a3 (5 0) (4 0) secondary
.model secondary lcouple (num_turns = 310)
One final note to be made about the two core model nodes is that certain parameters are available in one mode, but not in the other. In particular, the in_low, in_high, out_lower_limit, out_upper_limit, and hysteresis parameters are not available in PWL mode. Likewise, the H_array, B_array, area, and length values are unavailable in HYSTERESIS mode. The input domain and fraction parameters are common to both modes (though their behavior is somewhat different; for explanation of the input domain and fraction values for the HYSTERESIS mode, you should refer to the hysteresis code model discussion).
Controlled Sine Wave Oscillator
NAME_TABLE:
C_Function_Name: cm_sine
Spice_Model_Name: sine
Description: "controlled sine wave oscillator"
PORT_TABLE:
Port Name: cntl_in out
Description: "control input" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: cntl_array freq_array
Description: "control array" "frequency array"
Data_Type: real real
Default_Value: 0.0 1.0e3
Limits:  [0 ]
Vector: yes yes
Vector_Bounds: [2 ] cntl_array
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: out_low out_high
Description: "output peak low value" "output peak high value"
Data_Type: real real
Default_Value: 1.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
 Description:
This function is a controlled sine wave oscillator with parametrizable values of low and high peak output. It takes an input voltage or current value. This value is used as the independent variable in the piecewise linear curve described by the coordinate points of the cntl array and freq array pairs. From the curve, a frequency value is determined, and the oscillator will output a sine wave at that frequency. From the above, it is easy to see that array sizes of 2 for both the cntl array and the freq array will yield a linear variation of the frequency with respect to the control input. Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to the description of the piecewise linear controlled source, which uses a similar method to derive an output value given a control input.
Example SPICE Usage:
asine 1 2 in_sine
.model in_sine sine(cntl_array = [1 0 5 6]
+ freq_array=[10 10 1000 1000] out_low = 5.0
+ out_high = 5.0)
Controlled Triangle Wave Oscillator
NAME_TABLE:
C_Function_Name: cm_triangle
Spice_Model_Name: triangle
Description: "controlled triangle wave oscillator"
PORT_TABLE:
Port Name: cntl_in out
Description: "control input" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: cntl_array freq_array
Description: "control array" "frequency array"
Data_Type: real real
Default_Value: 0.0 1.0e3
Limits:  [0 ]
Vector: yes yes
Vector_Bounds: [2 ] cntl_array
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: out_low out_high
Description: "output peak low value" "output peak high value"
Data_Type: real real
Default_Value: 1.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: duty_cycle
Description: "rise time duty cycle"
Data_Type: real
Default_Value: 0.5
Limits: [1e10 0.999999999]
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
This function is a controlled triangle/ramp wave oscillator with parametrizable values of low and high peak output and rise time duty cycle. It takes an input voltage or current value. This value is used as the independent variable in the piecewise linear curve described by the coordinate points of the cntl_array and freq_array pairs.
From the curve, a frequency value is determined, and the oscillator will output a triangle wave at that frequency. From the above, it is easy to see that array sizes of 2 for both the cntl_array and the freq_array will yield a linear variation of the frequency with respect to the control input. Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to the description of the piecewise linear controlled source, which uses a similar method to derive an output value given a control input.
Example SPICE Usage:
ain 1 2 ramp1
.model ramp1 triangle(cntl_array = [1 0 5 6]
+ freq_array=[10 10 1000 1000] out_low = 5.0
+ out_high = 5.0 duty_cycle = 0.9)
Controlled Square Wave Oscillator
NAME_TABLE:
C_Function_Name: cm_square
Spice_Model_Name: square
Description: "controlled square wave oscillator"
PORT_TABLE:
Port Name: cntl_in out
Description: "control input" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: cntl_array freq_array
Description: "control array" "frequency array"
Data_Type: real real
Default_Value: 0.0 1.0e3
Limits:  [0 ]
Vector: yes yes
Vector_Bounds: [2 ] cntl_array
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: out_low out_high
Description: "output peak low value" "output peak high value"
Data_Type: real real
Default_Value: 1.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER.TABLE:
Parameter_Name: duty_cycle rise_time
Description: "duty cycle" "output rise time"
Data_Type: real real
Default_Value: 0.5 1.0e9
Limits: [1e6 0.999999] 
Vector: no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: fall_time
Description: "output fall time"
Data_Type: real
Default_Value: 1.0e9
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
This function is a controlled square wave oscillator with parametrizable values of low and high peak output, duty cycle, rise time, and fall time. It takes an input voltage or current value. This value is used as the independent variable in the piecewise linear curve described by the coordinate points of the cntl_array and freq_array pairs. From the curve, a frequency value is determined, and the oscillator will output a square wave at that frequency.
From the above, it is easy to see that array sizes of 2 for both the cntl_array and the freq_array will yield a linear variation of the frequency with respect to the control input. Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to the description of the piecewise linear controlled source, which uses a similar method to derive an output value given a control input.
Example SPICE Usage:
ain 1 2 pulse1
.model pulse1 square(cntl_array = [1 0 5 6]
+ freq_array=[10 10 1000 1000] out_low = 0.0
+ out_high = 4.5 duty_cycle = 0.2
+ rise_time = 1e6 fall_time = 2e6)
Controlled OneShot
NAME_TABLE:
C_Function_Name: cm_oneshot
Spice_Model_Name: oneshot
Description: "controlled oneshot"
PORT_TABLE:
Port Name: clk cntl_in
Description: "clock input" "control input"
Direction: in in
Default_Type: v v
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
Vector: no no
Vector_Bounds:  
Null_Allowed: no yes
PORT_TABLE:
Port Name: clear out
Description: "clear signal" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes no
PARAMETER_TABLE:
Parameter_Name: clk_trig retrig
Description: "clock trigger value" "retrigger switch"
Data_Type: real boolean
Default_Value: 0.5 FALSE
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: no yes
PARAMETER_TABLE:
Parameter_Name: pos_edge_trig
Description: "positive/negative edge trigger switch"
Data_Type: boolean
Default_Value: TRUE
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: cntl_array pw_array
Description: "control array" "pulse width array"
Data_Type: real real
Default_Value: 0.0 1.0e6
Limits:  [0.00 ]
Vector: yes yes
Vector_Bounds:  cntl_array
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: out_low out_high
Description: "output low value" "output high value"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: fall_time rise_time
Description: "output fall time" "output rise time"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: rise_delay
Description: "output delay from trigger"
Data_Type: real
Default_Value: 1.0e9
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: fall_delay
Description: "output delay from pw"
Data_Type: real
Default_Value: 1.0e9
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
This function is a controlled oneshot with parametrizable values of low and high peak output, input trigger value level, delay, and output rise and fall times. It takes an input voltage or current value. This value is used as the independent variable in the piecewise linear curve described by the coordinate points of the cntl_array and pw_array pairs. From the curve, a pulse width value is determined. The oneshot will output a pulse of that width, triggered by the clock signal (rising or falling edge), delayed by the delay value, and with specified rise and fall times. A positive slope on the clear input will immediately terminate the pulse, which resets with its fall time.
From the above, it is easy to see that array sizes of 2 for both the cntl_array and the pw_array will yield a linear variation of the pulse width with respect to the control input. Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to the description of the piecewise linear controlled source, which uses a similar method to derive an output value given a control input.
Example SPICE Usage:
ain 1 2 3 4 pulse2
.model pulse2 oneshot(cntl_array = [1 0 10 11]
+ pw_array=[1e6 1e6 1e4 1e4]
+ clk_trig = 0.9 pos_edge_trig = FALSE
+ out_low = 0.0 out_high = 4.5
+ rise_delay = 20.09 fall_delay = 35.0e9)
Capacitance Meter
NAME_TABLE:
C_Function_Name: cm_cmeter
Spice_Model_Name: cmeter
Description: "capacitance meter"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: gain
Description: "gain"
Data_Type: real
Default_Value: 1.0
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The capacitance meter is a sensing device that is attached to a circuit node and produces as an output a scaled value equal to the total capacitance seen on its input multiplied by the gain parameter. This model is primarily intended as a building block for other models that must sense a capacitance value and alter their behavior based upon it.
Example SPICE Usage:
atest1 1 2 ctest
.model ctest cmeter(gain=1.0e12)
Inductance Meter
NAME_TABLE:
C_Function_Name: cm_lmeter
Spice_Model_Name: lmeter
Description: "inductance meter"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: v v
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: gain
Description: "gain"
Data_Type: real
Default_Value: 1.0
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The inductance meter is a sensing device that is attached to a circuit node and produces as an output a scaled value equal to the total inductance seen on its input multiplied by the gain parameter. This model is primarily intended as a building block for other models that must sense an inductance value and alter their behavior based upon it.
Example SPICE Usage:
atest2 1 2 ltest
.model ltest lmeter(gain=1.0e6)
Memristor
NAME_TABLE:
C_Function_Name: cm_memristor
Spice_Model_Name: memristor
Description: "Memristor Interface"
PORT_TABLE:
Port_Name: memris
Description: "memristor terminals"
Direction: inout
Default_Type: gd
Allowed_Types: [gd]
Vector: no
Vector_Bounds: 
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: rmin rmax
Description: "minimum resistance" "maximum resistance"
Data_Type: real real
Default_Value: 10.0 10000.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: rinit vt
Description: "initial resistance" "threshold"
Data_Type: real real
Default_Value: 7000.0 0.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: alpha beta
Description: "model parameter 1" "model parameter 2"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
 Description:
The memristor is a twoterminal resistor with memory, whose resistance depends on the time integral of the voltage across its terminals. rmin and rmax provide the lower and upper limits of the resistance, rinit is its starting value (no voltage applied so far). The voltage has to be above a threshold vt to become effective in changing the resistance. alpha and beta are two model parameters. The memristor code model is derived from a SPICE subcircuit published in [23].
Example SPICE Usage:
amen 1 2 memr
.model memr memristor (rmin=1k rmax=10k rinit=7k
+ alpha=0 beta=2e13 vt=1.6)
2D table model
NAME_TABLE:
C_Function_Name: cm_table2D
Spice_Model_Name: table2D
Description: "2D table model"
PORT_TABLE:
Port_Name: inx iny out
Description: "inputx" "inputy" "output"
Direction: in in out
Default_Type: v v i
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam] [v,vd,i,id]
Vector: no no no
Vector_Bounds:   
Null_Allowed: no no no
PARAMETER_TABLE:
Parameter_Name: order verbose
Description: "order" "verbose"
Data_Type: int int
Default_Value: 3 0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: offset gain
Description: "offset" "gain"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: file
Description: "file name"
Data_Type: string
Default_Value: "2Dtablemodel.txt"
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The 2D table model reads a matrix from file "file name" (default 2Dtablemodel.txt) which has x columns and y rows. Each x,y pair, addressed by inx and iny, yields an output value out. Linear interpolation is used for out, eno (essentially non oscillating) interpolation for its derivatives. Parameters offset (default 0) and gain (default 1) modify the output table values according to (offset + gain out). Parameter order (default 3) influences the calculation of the derivatives. Parameter verbose (default 0) yields test outputs, if set to 1 or 2. The table format is shown below. Be careful to include the data point inx = 0, iny = 0 into your table, because ngspice uses these during .OP computations. The x horizontal and y vertical address values have to increase monotonically.
Table Example:
* table source
* number of columns (x)
8
* number of rows (y)
9
* x horizontal (column) address values (real numbers)
1 0 1 2 3 4 5 6
* y vertical (row) address values (real numbers)
0.6 0 0.6 1.2 1.8 2.4 3.0 3.6 4.2
* table with output data (horizontally addressed by x, vertically by y)
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3
1 1 1 1 1 1 1 1
1 1.2 1.4 1.6 1.8 2 2.2 2.4
1 1.5 2 2.5 3 3.5 4 4.5
1 2 3 4 5 6 7 8
1 2.5 4 5.5 7 8.5 10 11.5
1 3 5 7 9 11 13 15
1 3.5 6 8.5 11 13.5 16 18.5
1 4 7 10 13 16 19 22
 Description:
The usage example consists of two input voltages referenced to ground and a current source output with two floating nodes.
Example SPICE Usage:
atab inx iny %id(out1 out2) tabmod
.model tabmod table2d (offset=0.0 gain=1 order=3 file="tablesimple.txt")
3D table model
NAME_TABLE:
C_Function_Name: cm_table3D
Spice_Model_Name: table3D
Description: "3D table model"
PORT_TABLE:
Port_Name: inx iny inz
Description: "inputx" "inputy" "inputz"
Direction: in in in
Default_Type: v v v
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam] [v,vd,i,id,vnam]
Vector: no no no
Vector_Bounds:   
Null_Allowed: no no no
PORT_TABLE:
Port_Name: out
Description: "output"
Direction: out
Default_Type: i
Allowed_Types: [v,vd,i,id]
Vector: no
Vector_Bounds: 
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: order verbose
Description: "order" "verbose"
Data_Type: int int
Default_Value: 3 0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: offset gain
Description: "offset" "gain"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: file
Description: "file name"
Data_Type: string
Default_Value: "3Dtablemodel.txt"
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The 3D table model reads a matrix from file "file name" (default 3Dtablemodel.txt) which has x columns, y rows per table and z tables. Each x,y,z triple, addressed by inx, iny, and inz, yields an output value out. Linear interpolation is used for out, eno (essentially non oscillating) interpolation for its derivatives. Parameters offset (default 0) and gain (default 1) modify the output table values according to (offset + gain out). Parameter order (default 3) influences the calculation of the derivatives. Parameter verbose (default 0) yields test outputs, if set to 1 or 2. The table format is shown below. Be careful to include the data point inx = 0, iny = 0, inz = 0 into your table, because ngspice needs these to for the .OP calculation. The x horizontal, y vertical, and z table address values have to increase monotonically.
Table Example:
* 3D table for nmos bsim 4, W=10um, L=0.13um
*x
39
*y
39
*z
11
*x (drain voltage)
0.1 0.05 0 0.05 0.1 0.15 0.2 0.25 ...
*y (gate voltage)
0.1 0.05 0 0.05 0.1 0.15 0.2 0.25 ...
*z (substrate voltage)
1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0.2
*table 1.8
4.50688E10 4.50613E10 4.50601E10 4.50599E10 ...
4.49622E10 4.49267E10 4.4921E10 4.49202E10 ...
4.50672E10 4.49099E10 4.48838E10 4.48795E10 ...
4.55575E10 4.4953E10 4.48435E10 4.48217E10 ...
...
*table 1.6
3.10015E10 3.09767E10 3.0973E10 3.09724E10 ...
3.09748E10 3.08524E10 3.08339E10 3.08312E10 ...
...
*table 1.4
2.04848E10 2.04008E10 2.03882E10 ...
2.07275E10 2.03117E10 2.02491E10 ...
...
 Description:
The usage example simulates a NMOS transistor with independent drain, gate and bulk nodes, referenced to source. Parameter gain may be used to emulate transistor width, with respect to the table transistor.
Example SPICE Usage:
amos1 %vd(d s) %vd(g s) %vd(b s) %id(d s) mostable1
.model mostable1 table3d (offset=0.0 gain=0.5 order=3
+ verbose=1 file="table3Dbsim4n.txt")
2D table model
NAME_TABLE:
C_Function_Name: cm_table2D
Spice_Model_Name: table2D
Description: "2D table model"
PORT_TABLE:
Port_Name: inx iny out
Description: "inputx" "inputy" "output"
Direction: in in out
Default_Type: v v i
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam] [v,vd,i,id]
Vector: no no no
Vector_Bounds:   
Null_Allowed: no no no
PARAMETER_TABLE:
Parameter_Name: order verbose
Description: "order" "verbose"
Data_Type: int int
Default_Value: 3 0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: offset gain
Description: "offset" "gain"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: file
Description: "file name"
Data_Type: string
Default_Value: "2Dtablemodel.txt"
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The 2D table model reads a matrix from file "file name" (default 2Dtablemodel.txt) which has x columns and y rows. Each x,y pair, addressed by inx and iny, yields an output value out. Linear interpolation is used for out, eno (essentially non oscillating) interpolation for its derivatives. Parameters offset (default 0) and gain (default 1) modify the output table values according to (offset + gain out). Parameter order (default 3) influences the calculation of the derivatives. Parameter verbose (default 0) yields test outputs, if set to 1 or 2. The table format is shown below. Be careful to include the data point inx = 0, iny = 0 into your table, because ngspice uses these during .OP computations. The x horizontal and y vertical address values have to increase monotonically.
Table Example:
* table source
* number of columns (x)
8
* number of rows (y)
9
* x horizontal (column) address values (real numbers)
1 0 1 2 3 4 5 6
* y vertical (row) address values (real numbers)
0.6 0 0.6 1.2 1.8 2.4 3.0 3.6 4.2
* table with output data (horizontally addressed by x, vertically by y)
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3
1 1 1 1 1 1 1 1
1 1.2 1.4 1.6 1.8 2 2.2 2.4
1 1.5 2 2.5 3 3.5 4 4.5
1 2 3 4 5 6 7 8
1 2.5 4 5.5 7 8.5 10 11.5
1 3 5 7 9 11 13 15
1 3.5 6 8.5 11 13.5 16 18.5
1 4 7 10 13 16 19 22
 Description:
The usage example consists of two input voltages referenced to ground and a current source output with two floating nodes.
Example SPICE Usage:
atab inx iny %id(out1 out2) tabmod
.model tabmod table2d (offset=0.0 gain=1 order=3 file="tablesimple.txt")
3D table model
NAME_TABLE:
C_Function_Name: cm_table3D
Spice_Model_Name: table3D
Description: "3D table model"
PORT_TABLE:
Port_Name: inx iny inz
Description: "inputx" "inputy" "inputz"
Direction: in in in
Default_Type: v v v
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam] [v,vd,i,id,vnam]
Vector: no no no
Vector_Bounds:   
Null_Allowed: no no no
PORT_TABLE:
Port_Name: out
Description: "output"
Direction: out
Default_Type: i
Allowed_Types: [v,vd,i,id]
Vector: no
Vector_Bounds: 
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: order verbose
Description: "order" "verbose"
Data_Type: int int
Default_Value: 3 0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: offset gain
Description: "offset" "gain"
Data_Type: real real
Default_Value: 0.0 1.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: file
Description: "file name"
Data_Type: string
Default_Value: "3Dtablemodel.txt"
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The 3D table model reads a matrix from file "file name" (default 3Dtablemodel.txt) which has x columns, y rows per table and z tables. Each x,y,z triple, addressed by inx, iny, and inz, yields an output value out. Linear interpolation is used for out, eno (essentially non oscillating) interpolation for its derivatives. Parameters offset (default 0) and gain (default 1) modify the output table values according to (offset + gain out). Parameter order (default 3) influences the calculation of the derivatives. Parameter verbose (default 0) yields test outputs, if set to 1 or 2. The table format is shown below. Be careful to include the data point inx = 0, iny = 0, inz = 0 into your table, because ngspice needs these to for the .OP calculation. The x horizontal, y vertical, and z table address values have to increase monotonically.
Table Example:
* 3D table for nmos bsim 4, W=10um, L=0.13um
*x
39
*y
39
*z
11
*x (drain voltage)
0.1 0.05 0 0.05 0.1 0.15 0.2 0.25 ...
*y (gate voltage)
0.1 0.05 0 0.05 0.1 0.15 0.2 0.25 ...
*z (substrate voltage)
1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0.2
*table 1.8
4.50688E10 4.50613E10 4.50601E10 4.50599E10 ...
4.49622E10 4.49267E10 4.4921E10 4.49202E10 ...
4.50672E10 4.49099E10 4.48838E10 4.48795E10 ...
4.55575E10 4.4953E10 4.48435E10 4.48217E10 ...
...
*table 1.6
3.10015E10 3.09767E10 3.0973E10 3.09724E10 ...
3.09748E10 3.08524E10 3.08339E10 3.08312E10 ...
...
*table 1.4
2.04848E10 2.04008E10 2.03882E10 ...
2.07275E10 2.03117E10 2.02491E10 ...
...
 Description:
The usage example simulates a NMOS transistor with independent drain, gate and bulk nodes, referenced to source. Parameter gain may be used to emulate transistor width, with respect to the table transistor.
Example SPICE Usage:
amos1 %vd(d s) %vd(g s) %vd(b s) %id(d s) mostable1
.model mostable1 table3d (offset=0.0 gain=0.5 order=3
+ verbose=1 file="table3Dbsim4n.txt")
Simple Diode Model
NAME_TABLE:
C_Function_Name: cm_sidiode
Spice_Model_Name: sidiode
Description: "simple diode"
PORT_TABLE:
Port_Name: ds
Description: "diode port"
Direction: inout
Default_Type: gd
Allowed_Types: [gd]
Vector: no
Vector_Bounds: 
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: ron roff
Description: "resistance onstate" "resistance offstate"
Data_Type: real real
Default_Value: 1 1
1
If roff is not given, ron is the default
Limits: [1e6  ] [1e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: vfwd vrev
Description: "forward voltage" "reverse breakdown voltage"
Data_Type: real real
Default_Value: 0. 1e30
Limits: [0. ] [0. ]
Vector: no no
Vector Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: ilimit revilimit
Description: "limit of oncurrent" "limit of breakdown current"
Data_Type: real real
Default_Value: 1e30 1e30
Limits: [1e15 ] [1e15 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: epsilon revepsilon
Description: "width quadrat. reg. 1" "width quadratic region 2"
Data_Type: real real
Default_Value: 0. 0.
Limits: [0. ] [0. ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: rrev
Description: "resistance in breakdown"
Data_Type: real
Default_Value: 0.
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
STATIC_VAR_TABLE:
Static_Var_Name: locdata
Data_Type: pointer
Description: "table with constants"
This is a model for a simple diode. Three regions are modelled as linear I(V) curves: Reverse (breakdown) current with Rrev starting at Vrev into the negative direction, Off current with Roff between Vrev and Vfwd and an On region with Ron, staring at Vfwd. The interface between the regions is described by a quadratic function, the width of the interface region is determined by Revepsilon and Epsilon. Current limits in the reverse breakdown (Revilimit) and in the forward (on) state (Ilimit) may be set. The interface is a tanh function. Thus the first derivative of the I(V) curve is continuous. All parameter values are entered as positive numbers. A diode capacitance is not modelled.
Example SPICE Usage:
a1 a k ds1
.model ds1 sidiode(Roff=1000 Ron=0.7 Rrev=0.2 Vfwd=1
+ Vrev=10 Revepsilon=0.2 Epsilon=0.2 Ilimit=7 Revilimit=7)
Hybrid Models
The following hybrid models are supplied with XSPICE. The descriptions included below consist of the model Interface Specification File and a description of the model's operation. This is followed by an example of a simulatordeck placement of the model, including the .MODEL card and the specification of all available parameters.
A note should be made with respect to the use of hybrid models for other than simple digitaltoanalog and analogtodigital translations. The hybrid models represented in this section address that specific need, but in the development of userdefined nodes you may find a need to translate not only between digital and analog nodes, but also between real and digital, real and int, etc. In most cases such translations will not need to be as involved or as detailed as shown in the following.
DigitaltoAnalog Node Bridge
NAME_TABLE:
C_Function_Name: cm_dac_bridge
Spice_Model_Name: dac_bridge
Description: "digitaltoanalog node bridge"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: d v
Allowed_Types: [d] [v,vd,i,id,d]
Vector: yes yes
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: out_low
Description: "0valued analog output"
Data_Type: real
Default_Value: 0.0
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: out_high
Description: "1valued analog output"
Data_Type: real
Default_Value: 1.0
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: out_undef input_load
Description: "Uvalued analog output" "input load (F)"
Data_Type: real real
Default_Value: 0.5 1.0e12
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: t_rise t_fall
Description: "rise time 0>1" "fall time 1>0"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
 Description:
The dac_bridge is the first of two node bridge devices designed to allow for the ready transfer of digital information to analog values and back again. The second device is the adc_bridge (which takes an analog value and maps it to a digital one).The dac_bridge takes as input a digital value from a digital node. This value by definition may take on only one of the values `0', `1' or `U'. The dac_bridge then outputs the value out_low, out_high or out_undef, or ramps linearly toward one of these `final' values from its current analog output level. The speed at which this ramping occurs depends on the values of t_rise and t_fall. These parameters are interpreted by the model such that the rise or fall slope generated is always constant. Note that the dac_bridge includes test code in its cfunc.mod file for determining the presence of the out_undef parameter. If this parameter is not specified by you, and if out_high and out_low values are specified, then out_undef is assigned the value of the arithmetic mean of out_high and out_low**.** This simplifies coding of output buffers, where typically a logic family will include an out_low and out_high voltage, but not an out_undef value. This model also posts an input load value (in farads) based on the parameter input load.
Example SPICE Usage:
abridge1 [7] [2] dac1
.model dac1 dac_bridge(out_low = 0.7 out_high = 3.5 out_undef = 2.2
+ input_load = 5.0e12 t_rise = 50e9
+ t_fall = 20e9)
AnalogtoDigital Node Bridge
NAME_TABLE:
C_Function_Name: cm_adc_bridge
Spice_Model_Name: adc_bridge
Description: "analogtodigital node bridge"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: v d
Allowed_Types: [v,vd,i,id,d] [d]
Vector: yes yes
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: in_low
Description: "maximum 0valued analog input"
Data_Type: real
Default_Value: 1.0
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: in_high
Description: "minimum 1valued analog input"
Data_Type: real
Default_Value: 2.0
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
 Description:
The adc_bridge is one of two node bridge devices designed to allow for the ready transfer of analog information to digital values and back again. The second device is the dac_bridge (which takes a digital value and maps it to an analog one). The adc_bridge takes as input an analog value from an analog node. This value by definition may be in the form of a voltage, or a current. If the input value is less than or equal to in_low, then a digital output value of `0' is generated. If the input is greater than or equal to in_high, a digital output value of `1' is generated. If neither of these is true, then a digital `UNKNOWN' value is output. Note that unlike the case of the dac_bridge, no ramping time or delay is associated with the adc_bridge. Rather, the continuous ramping of the input value provides for any associated delays in the digitized signal.
Example SPICE Usage:
abridge2 [1] [8] adc_buff
.model adc_buff adc_bridge(in_low = 0.3 in_high = 3.5)
Controlled Digital Oscillator
NAME_TABLE:
C_Function_Name: cm_d_osc
Spice_Model_Name: d_osc
Description: "controlled digital oscillator"
PORT_TABLE:
Port Name: cntl_in out
Description: "control input" "output"
Direction: in out
Default_Type: v d
Allowed_Types: [v,vd,i,id] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: cntl_array freq_array
Description: "control array" "frequency array"
Data_Type: real real
Default_Value: 0.0 1.0e6
Limits:  [0 ]
Vector: yes yes
Vector_Bounds: [2 ] cntl_array
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: duty_cycle init_phase
Description: "duty cycle" "initial phase of output"
Data_Type: real real
Default_Value: 0.5 0
Limits: [1e6 0.999999] [180.0 +360.0]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1e9 1e9
Limits: [0 ] [0 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
 Description:
The digital oscillator is a hybrid model that accepts as input a voltage or current. This input is compared to the voltagetofrequency transfer characteristic specified by the cntl_array/freq_array coordinate pairs, and a frequency is obtained that represents a linear interpolation or extrapolation based on those pairs. A digital timevarying signal is then produced with this fundamental frequency.
The output waveform, which is the equivalent of a digital clock signal, has rise and fall delays that can be specified independently. In addition, the duty cycle and the phase of the waveform are also variable and can be set by you.
Example SPICE Usage:
a5 1 8 var_clock
.model var_clock d_osc(cntl_array = [2 1 1 2]
+ freq_array = [1e3 1e3 10e3 10e3]
+ duty_cycle = 0.4 init_phase = 180.0
+ rise_delay = 10e9 fall_delay=8e9)
Node bridge from digital to real with enable
NAME_TABLE:
Spice_Model_Name: d_to_real
C_Function_Name: ucm_d_to_real
Description: "Node bridge from digital to real with enable"
PORT_TABLE:
Port_Name: in enable out
Description: "input" "enable" "output"
Direction: in in out
Default_Type: d d real
Allowed_Types: [d] [d] [real]
Vector: no no no
Vector_Bounds:   
Null_Allowed: no yes no
PARAMETER_TABLE:
Parameter_Name: zero one delay
Description: "value for 0" "value for 1" "delay"
Data_Type: real real real
Default_Value: 0.0 1.0 1e9
Limits:   [1e15 ]
Vector: no no no
Vector_Bounds:   
Null_Allowed: yes yes yes
A Z**1 block working on real data
NAME_TABLE:
Spice_Model_Name: real_delay
C_Function_Name: ucm_real_delay
Description: "A Z ** 1 block working on real data"
PORT_TABLE:
Port_Name: in clk out
Description: "input" "clock" "output"
Direction: in in out
Default_Type: real d real
Allowed_Types: [real] [d] [real]
Vector: no no no
Vector_Bounds:   
Null_Allowed: no no no
PARAMETER_TABLE:
Parameter_Name: delay
Description: "delay from clk to out"
Data_Type: real
Default_Value: 1e9
Limits: [1e15 ]
Vector: no
Vector_Bounds: 
Null_Allowed: yes
A gain block for eventdriven real data
NAME_TABLE:
Spice_Model_Name: real_gain
C_Function_Name: ucm_real_gain
Description: "A gain block for eventdriven real data"
PORT_TABLE:
Port_Name: in out
Description: "input" "output"
Direction: in out
Default_Type: real real
Allowed_Types: [real] [real]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: in_offset gain out_offset
Description: "input offset" "gain" "output offset"
Data_Type: real real real
Default_Value: 0.0 1.0 0.0
Limits:   
Vector: no no no
Vector_Bounds:   
Null_Allowed: yes yes yes
PARAMETER_TABLE:
Parameter_Name: delay ic
Description: "delay" "initial condition"
Data_Type: real real
Default_Value: 1.0e9 0.0
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
Node bridge from real to analog voltage
NAME_TABLE:
Spice_Model_Name: real_to_v
C_Function_Name: ucm_real_to_v
Description: "Node bridge from real to analog voltage"
PORT_TABLE:
Port_Name: in out
Description: "input" "output"
Direction: in out
Default_Type: real v
Allowed_Types: [real] [v, vd, i, id]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: gain transition_time
Description: "gain" "output transition time"
Data_Type: real real
Default_Value: 1.0 1e9
Limits:  [1e15 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
Digital Models
The following digital models are supplied with XSPICE. The descriptions included below consist of an example model Interface Specification File and a description of the model's operation. This is followed by an example of a simulatordeck placement of the model, including the .MODEL card and the specification of all available parameters. Note that these models have not been finalized at this time.
Some information common to all digital models and/or digital nodes is included here. The following are general rules that should make working with digital nodes and models more straightforward:
 All digital nodes are initialized to ZERO at the start of a simulation (i.e., when INIT=TRUE). This means that a model need not post an explicit value to an output node upon initialization if its output would normally be a ZERO (although posting such would certainly cause no harm).
 Digital nodes may have one out of twelve possible node values. See 12.5.1 for details.
 Digital models typically have defined their rise and fall delays for their output signals. A capacitive input load value may be defined as well to determine a loaddependent delay, but is currently not used in any code model (see 28.7.1.4).
 Several commands are available for outputting data, e.g. eprint, edisplay, and eprvcd. Digital inputs may be read from files. Please see Chapt. 12.5.4 for more details.
 Hybrid models (see Chapt. 12.3) provide an interface between the digital event driven world and the analog world of ngspice to enable true mixed mode simulation.
Buffer
NAME_TABLE:
C_Function_Name: cm_d_buffer
Spice_Model_Name: d_buffer
Description: "digital onebitwide buffer"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: input_load
Description: "input load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The buffer is a singleinput, singleoutput digital buffer that produces as output a timedelayed copy of its input. The delays associated with an output rise and those associated with an output fall may be different. The model also posts an input load value (in farads) based on the parameter input load. The output of this model does not, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays.
Example SPICE Usage:
a6 1 8 buff1
.model buff1 d_buffer(rise_delay = 0.5e9 fall_delay = 0.3e9
+ input_load = 0.5e12)
Inverter
NAME_TABLE:
C_Function_Name: cm_d_inverter
Spice_Model_Name: d_inverter
Description: "digital onebitwide inverter"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: input_load
Description: "input load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The inverter is a singleinput, singleoutput digital inverter that produces as output an inverted, timedelayed copy of its input. The delays associated with an output rise and those associated with an output fall may be specified independently. The model also posts an input load value (in farads) based on the parameter input load. The output of this model does not, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays.
Example SPICE Usage:
a6 1 8 inv1
.model inv1 d_inverter(rise_delay = 0.5e9 fall_delay = 0.3e9
+ input_load = 0.5e12)
And
NAME_TABLE:
C_Function_Name: cm_d_and
Spice_Model_Name: d_and
Description: "digital `and' gate"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: yes no
Vector_Bounds: [2 ] 
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: input_load
Description: "input load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The digital and gate is an ninput, singleoutput and gate that produces an active `1' value if, and only if, all of its inputs are also `1' values. If ANY of the inputs is a `0', the output will also be a `0'; if neither of these conditions holds, the output will be unknown. The delays associated with an output rise and those associated with an output fall may be specified independently. The model also posts an input load value (in farads) based on the parameter input load. The output of this model does not, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays.
Example SPICE Usage:
a6 [1 2] 8 and1
.model and1 d_and(rise_delay = 0.5e9 fall_delay = 0.3e9
+ input_load = 0.5e12)
Nand
NAME_TABLE:
C_Function_Name: cm_d_nand
Spice_Model_Name: d_nand
Description: "digital `nand' gate"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: yes no
Vector_Bounds: [2 ] 
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: input_load
Description: "input load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The digital nand gate is an ninput, singleoutput nand gate that produces an active `0' value if and only if all of its inputs are `1' values. If ANY of the inputs is a `0', the output will be a `1'; if neither of these conditions holds, the output will be unknown. The delays associated with an output rise and those associated with an output fall may be specified independently. The model also posts an input load value (in farads) based on the parameter input load. The output of this model does not, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays.
Example SPICE Usage:
a6 [1 2 3] 8 nand1
.model nand1 d_nand(rise_delay = 0.5e9 fall_delay = 0.3e9
+ input_load = 0.5e12)
Or
NAME_TABLE:
C_Function_Name: cm_d_or
Spice_Model_Name: d_or
Description: "digital `or' gate"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: yes no
Vector_Bounds: [2 ] 
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: input_load
Description: "input load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The digital or gate is an ninput, singleoutput or gate that produces an active `1' value if at least one of its inputs is a `1' value. The gate produces a `0' value if all inputs are `0'; if neither of these two conditions holds, the output is unknown. The delays associated with an output rise and those associated with an output fall may be specified independently. The model also posts an input load value (in farads) based on the parameter input load. The output of this model does not, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays.
Example SPICE Usage:
a6 [1 2 3] 8 or1
.model or1 d_or(rise_delay = 0.5e9 fall_delay = 0.3e9
+ input_load = 0.5e12)
Nor
NAME_TABLE:
C_Function_Name: cm_d_nor
Spice_Model_Name: d_nor
Description: "digital `nor' gate"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: yes no
Vector_Bounds: [2 ] 
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: input_load
Description: "input load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The digital nor gate is an ninput, singleoutput nor gate that produces an active `0' value if at least one of its inputs is a `1' value. The gate produces a `0' value if all inputs are `0'; if neither of these two conditions holds, the output is unknown. The delays associated with an output rise and those associated with an output fall may be specified independently. The model also posts an input load value (in farads) based on the parameter input load. The output of this model does not, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays.
Example SPICE Usage:
anor12 [1 2 3 4] 8 nor12
.model nor12 d_nor(rise_delay = 0.5e9 fall_delay = 0.3e9
+ input_load = 0.5e12)
Xor
NAME_TABLE:
C_Function_Name: cm_d_xor
Spice_Model_Name: d_xor
Description: "digital exclusiveor gate"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: yes no
Vector_Bounds: [2 ] 
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: input_load
Description: "input load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The digital xor gate is an ninput, singleoutput xor gate that produces an active `1' value if an odd number of its inputs are also `1' values. The delays associated with an output rise and those associated with an output fall may be specified independently.
The model also posts an input load value (in farads) based on the parameter input load. The output of this model does not, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays. Note also that to maintain the technologyindependence of the model, any UNKNOWN input, or any floating input causes the output to also go UNKNOWN.
Example SPICE Usage:
a9 [1 2] 8 xor3
.model xor3 d_xor(rise_delay = 0.5e9 fall_delay = 0.3e9
+ input_load = 0.5e12)
Xnor
NAME_TABLE:
C_Function_Name: cm_d_xnor
Spice_Model_Name: d_xnor
Description: "digital exclusivenor gate"
PORT_TABLE:
Port Name: in out
Description: "input" "output"
Direction: in out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: yes no
Vector_Bounds: [2 ] 
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: input_load
Description: "input load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The digital xnor gate is an ninput, singleoutput xnor gate that produces an active `0' value if an odd number of its inputs are also `1' values. It produces a `1' output when an even number of `1' values occurs on its inputs. The delays associated with an output rise and those associated with an output fall may be specified independently. The model also posts an input load value (in farads) based on the parameter input load. The output of this model does not, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays. Note also that to maintain the technologyindependence of the model, any UNKNOWN input, or any floating input causes the output to also go UNKNOWN.
Example SPICE Usage:
a9 [1 2] 8 xnor3
.model xnor3 d_xnor(rise_delay = 0.5e9 fall_delay = 0.3e9
+ input_load = 0.5e12)
Tristate
NAME_TABLE:
C_Function_Name: cm_d_tristate
Spice_Model_Name: d_tristate
Description: "digital tristate buffer"
PORT_TABLE:
Port Name: in enable out
Description: "input" "enable" "output"
Direction: in in out
Default_Type: d d d
Allowed_Types: [d] [d] [d]
Vector: no no no
Vector_Bounds:   
Null_Allowed: no no no
PARAMETER_TABLE:
Parameter_Name: delay
Description: "delay"
Data_Type: real
Default_Value: 1.0e9
Limits: [1.0e12 ]
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: input_load
Description: "input load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: enable_load
Description: "enable load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The digital tristate is a simple tristate gate that can be configured to allow for opencollector behavior, as well as standard tristate behavior. The state seen on the input line is reflected in the output. The state seen on the enable line determines the strength of the output. Thus, a ONE forces the output to its state with a STRONG strength. A ZERO forces the output to go to a HI_IMPEDANCE strength. The delays associated with an output state or strength change cannot be specified independently, nor may they be specified independently for rise or fall conditions; other gate models may be used to provide such delays if needed. The model posts input and enable load values (in farads) based on the parameters input load and enable. The output of this model does not, however, respond to the total loading it sees on its output; it will always drive the output with the specified delay. Note also that to maintain the technologyindependence of the model, any UNKNOWN input, or any floating input causes the output to also go UNKNOWN. Likewise, any UNKNOWN input on the enable line causes the output to go to an UNDETERMINED strength value.
Example SPICE Usage:
a9 1 2 8 tri7
.model tri7 d_tristate(delay = 0.5e9 input_load = 0.5e12
+ enable_load = 0.5e12)
Pullup
NAME_TABLE:
C_Function_Name: cm_d_pullup
Spice_Model_Name: d_pullup
Description: "digital pullup resistor"
PORT_TABLE:
Port Name: out
Description: "output"
Direction: out
Default_Type: d
Allowed_Types: [d]
Vector: no
Vector_Bounds: 
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: load
Description: "load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The digital pullup resistor is a device that emulates the behavior of an analog resistance value tied to a high voltage level. The pullup may be used in conjunction with tristate buffers to provide opencollector wired or constructs, or any other logical constructs that rely on a resistive pullup common to many tristated output devices. The model posts an input load value (in farads) based on the parameter load.
Example SPICE Usage:
a2 9 pullup1
.model pullup1 d_pullup(load = 20.0e12)
Pulldown
NAME_TABLE:
C_Function_Name: cm_d_pulldown
Spice_Model_Name: d_pulldown
Description: "digital pulldown resistor"
PORT_TABLE:
Port Name: out
Description: "output"
Direction: out
Default_Type: d
Allowed_Types: [d]
Vector: no
Vector_Bounds: 
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: load
Description: "load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The digital pulldown resistor is a device that emulates the behavior of an analog resistance value tied to a low voltage level. The pulldown may be used in conjunction with tristate buffers to provide opencollector wired or constructs, or any other logical constructs that rely on a resistive pulldown common to many tristated output devices. The model posts an input load value (in farads) based on the parameter load.
Example SPICE Usage:
a4 9 pulldown1
.model pulldown1 d_pulldown(load = 20.0e12)
D Flip Flop
NAME_TABLE:
C_Function_Name: cm_d_dff
Spice_Model_Name: d_dff
Description: "digital dtype flip flop"
PORT_TABLE:
Port Name: data clk
Description: "input data" "clock"
Direction: in in
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PORT_TABLE:
Port Name: set reset
Description: "asynch. set" "asynch. reset"
Direction: in in
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PORT_TABLE:
Port Name: out Nout
Description: "data output" "inverted data output"
Direction: out out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: clk_delay set_delay
Description: "delay from clk" "delay from set"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: reset_delay ic
Description: "delay from reset" "output initial state"
Data_Type: real int
Default_Value: 1.0e9 0
Limits: [1.0e12 ] [0 2]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: data_load clk_load
Description: "data load value (F)" "clk load value (F)"
Data_Type: real real
Default_Value: 1.0e12 1.0e12
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: set_load reset_load
Description: "set load value (F)" "reset load (F)"
Data_Type: real real
Default_Value: 1.0e12 1.0e12
Limits:  
Vector: no no
Vector.Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
 Description:
The digital dtype flip flop is a onebit, edgetriggered storage element that will store data whenever the clk input line transitions from low to high (ZERO to ONE). In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_dff have separate load values and delays associated with them. Additionally, you may specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies.
Note that any UNKNOWN input on the set or reset lines immediately results in an UNKNOWN output.
Example SPICE Usage:
a7 1 2 3 4 5 6 flop1
.model flop1 d_dff(clk_delay = 13.0e9 set_delay = 25.0e9
+ reset_delay = 27.0e9 ic = 2 rise_delay = 10.0e9
+ fall_delay = 3e9)
JK Flip Flop
NAME_TABLE:
C_Function_Name: cm_d_jkff
Spice_Model_Name: d_jkff
Description: "digital jktype flip flop"
PORT_TABLE:
Port Name: j k
Description: "j input" "k input"
Direction: in in
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PORT_TABLE:
Port Name: clk
Description: "clock"
Direction: in
Default_Type: d
Allowed_Types: [d]
Vector: no
Vector_Bounds: 
Null_Allowed: no
PORT_TABLE:
Port Name: set reset
Description: "asynchronous set" "asynchronous reset"
Direction: in in
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PORT_TABLE:
Port Name: out Nout
Description: "data output" "inverted data output"
Direction: out out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: clk_delay set_delay
Description: "delay from clk" "delay from set"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: reset_delay ic
Description: "delay from reset" "output initial state"
Data_Type: real int
Default_Value: 1.0e9 0
Limits: [1.0e12 ] [0 2]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: jk_load clk_load
Description: "j,k load values (F)" "clk load value (F)"
Data_Type: real real
Default_Value: 1.0e12 1.0e12
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: set_load reset_load
Description: "set load value (F)" "reset load (F)"
Data_Type: real real
Default_Value: 1.0e12 1.0e12
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
 Description:
The digital jktype flip flop is a onebit, edgetriggered storage element that will store data whenever the clk input line transitions from low to high (ZERO to ONE). In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_jkff have separate load values and delays associated with them. Additionally, you may specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies.
Note that any UNKNOWN inputs other than j or k cause the output to go UNKNOWN automatically.
Example SPICE Usage:
a8 1 2 3 4 5 6 7 flop2
.model flop2 d_jkff(clk_delay = 13.0e9 set_delay = 25.0e9
+ reset_delay = 27.0e9 ic = 2 rise_delay = 10.0e9
+ fall_delay = 3e9)
Toggle Flip Flop
NAME_TABLE:
C_Function_Name: cm_d_tff
Spice_Model_Name: d_tff
Description: "digital toggle flip flop"
PORT_TABLE:
Port Name: t clk
Description: "toggle input" "clock"
Direction: in in
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PORT_TABLE:
Port Name: set reset
Description: "set" "reset"
Direction: in in
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PORT.TABLE:
Port Name: out Nout
Description: "data output" "inverted data output"
Direction: out out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: clk_delay set_delay
Description: "delay from clk" "delay from set"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: reset_delay ic
Description: "delay from reset" "output initial state"
Data_Type: real int
Default_Value: 1.0e9 0
Limits: [1.0e12 ] [0 2]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: t_load clk_load
Description: "toggle load value (F)" "clk load value (F)"
Data_Type: real real
Default_Value: 1.0e12 1.0e12
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: set_load reset_load
Description: "set load value (F)" "reset load (F)"
Data_Type: real real
Default.Value: 1.0e12 1.0e12
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
 Description:
The digital toggletype flip flop is a onebit, edgetriggered storage element that will toggle its current state whenever the clk input line transitions from low to high (ZERO to ONE). In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_tff have separate load values and delays associated with them. Additionally, you may specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies.
Note that any UNKNOWN inputs other than t immediately cause the output to go UNKNOWN.
Example SPICE Usage:
a8 2 12 4 5 6 3 flop3
.model flop3 d_tff(clk_delay = 13.0e9 set_delay = 25.0e9
+ reset_delay = 27.0e9 ic = 2 rise_delay = 10.0e9
+ fall_delay = 3e9 t_load = 0.2e12)
SetReset Flip Flop
NAME_TABLE:
C_Function_Name: cm_d_srff
Spice_Model_Name: d_srff
Description: "digital setreset flip flop"
PORT_TABLE:
Port Name: s r
Description: "set input" "reset input"
Direction: in in
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PORT_TABLE:
Port Name: clk
Description: "clock"
Direction: in
Default_Type: d
Allowed_Types: [d]
Vector: no
Vector_Bounds: 
Null_Allowed: no
PORT_TABLE:
Port Name: set reset
Description: "asynchronous set" "asynchronous reset"
Direction: in in
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PORT_TABLE:
Port Name: out Nout
Description: "data output" "inverted data output"
Direction: out out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: clk_delay set_delay
Description: "delay from clk" "delay from set"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: reset_delay ic
Description: "delay from reset" "output initial state"
Data_Type: real int
Default_Value: 1.0e9 0
Limits: [1.0e12 ] [0 2]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: sr_load clk_load
Description: "set/reset loads (F)" "clk load value (F)"
Data_Type: real real
Default_Value: 1.0e12 1.0e12
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: set_load reset_load
Description: "set load value (F)" "reset load (F)"
Data_Type: real real
Default_Value: 1.0e12 1.0e12
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
 Description:
The digital srtype flip flop is a onebit, edgetriggered storage element that will store data whenever the clk input line transitions from low to high (ZERO to ONE). The value stored (i.e., the out value) will depend on the s and r input pin values, and will be:
out=ONE if s=ONE and r=ZERO;
out=ZERO if s=ZERO and r=ONE;
out=previous value if s=ZERO and r=ZERO;
out=UNKNOWN if s=ONE and r=ONE;
In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_srff have separate load values and delays associated with them. You may also specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies.
Note that any UNKNOWN inputs other than s and r immediately cause the output to go UNKNOWN.
Example SPICE Usage:
a8 2 12 4 5 6 3 14 flop7
.model flop7 d_srff(clk_delay = 13.0e9 set_delay = 25.0e9
+ reset_delay = 27.0e9 ic = 2 rise_delay = 10.0e9
+ fall_delay = 3e9)
D Latch
NAME_TABLE:
C_Function_Name: cm_d_dlatch
Spice_Model_Name: d_dlatch
Description: "digital dtype latch"
PORT_TABLE:
Port Name: data enable
Description: "input data" "enable input"
Direction: in in
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PORT_TABLE:
Port Name: set reset
Description: "set" "reset"
Direction: in in
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PORT_TABLE:
Port Name: out Nout
Description: "data output" "inverter data output"
Direction: out out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: data_delay
Description: "delay from data"
Data_Type: real
Default_Value: 1.0e9
Limits: [1.0e12 ]
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: enable_delay set_delay
Description: "delay from enable" "delay from SET"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: reset_delay ic
Description: "delay from RESET" "output initial state"
Data_Type: real boolean
Default_Value: 1.0e9 0
Limits: [1.0e12 ] 
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: data_load enable_load
Description: "data load (F)" "enable load value (F)"
Data_Type: real real
Default_Value: 1.0e12 1.0e12
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: set_load reset_load
Description: "set load value (F)" "reset load (F)"
Data_Type: real real
Default_Value: 1.0e12 1.0e12
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
 Description:
The digital dtype latch is a onebit, levelsensitive storage element that will output the value on the data line whenever the enable input line is high (ONE). The value on the data line is stored (i.e., held on the out line) whenever the enable line is low (ZERO).
In addition, asynchronous set and reset signals exist, and each of the four methods of changing the stored output of the d_dlatch (i.e., data changing with enable=ONE, enable changing to ONE from ZERO with a new value on data, raising set and raising reset) have separate delays associated with them. You may also specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies.
Note that any UNKNOWN inputs other than on the data line when enable=ZERO immediately cause the output to go UNKNOWN.
Example SPICE Usage:
a4 12 4 5 6 3 14 latch1
.model latch1 d_dlatch(data_delay = 13.0e9 enable_delay = 22.0e9
+ set_delay = 25.0e9
+ reset_delay = 27.0e9 ic = 2
+ rise_delay = 10.0e9 fall_delay = 3e9)
SetReset Latch
NAME_TABLE:
C_Function_Name: cm_d_srlatch
Spice_Model_Name: d_srlatch
Description: "digital srtype latch"
PORT_TABLE:
Port Name: s r
Description: "set" "reset"
Direction: in in
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PORT_TABLE:
Port Name: enable
Description: "enable"
Direction: in
Default_Type: d
Allowed_Types: [d]
Vector: no
Vector_Bounds: 
Null_Allowed: no
PORT_TABLE:
Port Name: set reset
Description: "set" "reset"
Direction: in in
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PORT_TABLE:
Port Name: out Nout
Description: "data output" "inverted data output"
Direction: out out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: sr_delay
Description: "delay from s or r input change"
Data_Type: real
Default_Value: 1.0e9
Limits: [1.0e12 ]
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: enable_delay set_delay
Description: "delay from enable" "delay from SET"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: reset_delay ic
Description: "delay from RESET" "output initial state"
Data_Type: real boolean
Default_Value: 1.0e9 0
Limits: [1.0e12 ] 
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: sr_load enable_load
Description: "s & r input loads (F)" "enable load value (F)"
Data_Type: real real
Default_Value: 1.0e12 1.0e12
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: set_load reset_load
Description: "set load value (F)" "reset load (F)"
Data_Type: real real
Default_Value: 1.0e12 1.0e12
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
 Description:
The digital srtype latch is a onebit, levelsensitive storage element that will output the value dictated by the state of the s and r pins whenever the enable input line is high (ONE). This value is stored (i.e., held on the out line) whenever the enable line is low (ZERO). The particular value chosen is as shown below:
s=ZERO, r=ZERO => out=current value (i.e., not change in output)
s=ZERO, r=ONE => out=ZERO
s=ONE, r=ZERO => out=ONE
s=ONE, r=ONE => out=UNKNOWN
Asynchronous set and reset signals exist, and each of the four methods of changing the stored output of the d srlatch (i.e., s/r combination changing with enable=ONE, enable changing to ONE from ZERO with an outputchanging combination of s and r, raising set and raising reset) have separate delays associated with them. You may also specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies.
Note that any UNKNOWN inputs other than on the s and r lines when enable=ZERO immediately cause the output to go UNKNOWN.
Example SPICE Usage:
a4 12 4 5 6 3 14 16 latch2
.model latch2 d_srlatch(sr_delay = 13.0e9 enable_delay = 22.0e9
+ set_delay = 25.0e9
+ reset_delay = 27.0e9 ic = 2
+ rise_delay = 10.0e9 fall_delay = 3e9)
State Machine
NAME_TABLE:
C_Function_Name: cm_d_state
Spice_Model_Name: d_state
Description: "digital state machine"
PORT_TABLE:
Port Name: in clk
Description: "input" "clock"
Direction: in in
Default_Type: d d
Allowed_Types: [d] [d]
Vector: yes no
Vector_Bounds: [1 ] 
Null_Allowed: yes no
PORT_TABLE:
Port Name: reset out
Description: "reset" "output"
Direction: in out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no yes
Vector_Bounds:  [1 ]
Null_Allowed: yes no
PARAMETER_TABLE:
Parameter_Name: clk_delay reset_delay
Description: "delay from CLK" "delay from RESET"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE: Parameter_Name: state_file
Description: "state transition specification file name"
Data_Type: string
Default_Value: "state.txt"
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: reset_state
Description: "default state on RESET & at DC"
Data_Type: int
Default_Value: 0
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: input_load
Description: "input loading capacitance (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: clk_load
Description: "clock loading capacitance (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: reset_load
Description: "reset loading capacitance (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The digital state machine provides for straightforward descriptions of clocked combinational logic blocks with a variable number of inputs and outputs and with an unlimited number of possible states. The model can be configured to behave as virtually any type of counter or clocked combinational logic block and can be used to replace very large digital circuit schematics with an identically functional but faster representation.
The d state model is configured through the use of a state definition file (state.in) that resides in a directory of your choosing. The file defines all states to be understood by the model, plus input bit combinations that trigger changes in state. An example state.in file is shown below:
 begin file 
* This is an example state.in file. This file
* defines a simple 2bit counter with one input. The
* value of this input determines whether the counter counts
* up (in = 1) or down (in = 0).
0 0s 0s 0 > 3
1 > 1
1 0s 1z 0 > 0
1 > 2
2 1z 0s 0 > 1
1 > 3
3 1z 1z 0 > 2
3 1z 1z 1 > 0
 end file 
Several attributes of the above file structure should be noted. First, all lines in the file must be one of four types. These are:
 A comment, beginning with a `*' in the first column.
 A header line, which is a complete description of the current state, the outputs corresponding to that state, an input value, and the state that the model will assume should that input be encountered. The first line of a state definition must always be a header line.
 A continuation line, which is a partial description of a state, consisting of an input value and the state that the model will assume should that input be encountered. Note that continuation lines may only be used after the initial header line definition for a state.
 A line containing nothing but whitespaces (space, formfeed, newline, carriage return, tab, vertical tab).
A line that is not one of the above will cause a fileloading error. Note that in the example shown, whitespace (any combination of blanks, tabs, commas) is used to separate values, and that the character > is used to underline the state transition implied by the input preceding it. This particular character is not critical in of itself, and can be replaced with any other character or nonbroken combination of characters that you prefer (e.g. ==>, >>, ':', resolves_to, etc.)
The order of the output and input bits in the file is important; the first column is always interpreted to refer to the 'zeroth' bit of input and output. Thus, in the file above, the output from state 1 sets out[0] to 0s, and out[1] to 1z.
The state numbers need not be in any particular order, but a state definition (which consists of the sum total of all lines that define the state, its outputs, and all methods by which a state can be exited) must be made on contiguous line numbers; a state definition cannot be broken into subblocks and distributed randomly throughout the file. On the other hand, the state definition can be broken up by as many comment lines as you desire.
Header files may be used throughout the state.in file, and continuation lines can be discarded completely if you so choose: continuation lines are primarily provided as a convenience.
Example SPICE Usage:
a4 [2 3 4 5] 1 12 [22 23 24 25 26 27 28 29] state1
.model state1 d_state(clk_delay = 13.0e9 reset_delay = 27.0e9
+ state_file = "newstate.txt" reset_state = 2)
 Note:
The file named by the parameter filename in state_file="filename" is sought after according to a search list described in12.1.3.
Frequency Divider
NAME_TABLE:
C_Function_Name: cm_d_fdiv
Spice_Model_Name: d_fdiv
Description: "digital frequency divider"
PORT_TABLE:
Port Name: freq_in freq_out
Description: "frequency input" "frequency output"
Direction: in out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no no
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: div_factor high_cycles
Description: "divide factor" "# of cycles for high out"
Data_Type: int int
Default_Value: 2 1
Limits: [1 ] [1 div_factor1]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: i_count
Description: "divider initial count value"
Data_Type: int
Default_Value: 0
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: yes yes
Vector_Bounds: in in
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: freq_in_load
Description: "freq_in load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The digital frequency divider is a programmable stepdown divider that accepts an arbitrary divisor (div_factor), a dutycycle term (high_cycles), and an initial count value (i_count). The generated output is synchronized to the rising edges of the input signal. Rise delay and fall delay on the outputs may also be specified independently.
Example SPICE Usage:
a4 3 7 divider
.model divider d_fdiv(div_factor = 5 high_cycles = 3
+ i_count = 4 rise_delay = 23e9
+ fall_delay = 9e9)
RAM
NAME_TABLE:
C_Function_Name: cm_d_ram
Spice_Model_Name: d_ram
Description: "digital randomaccess memory"
PORT_TABLE:
Port Name: data_in data_out
Description: "data input line(s)" "data output line(s)"
Direction: in out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: yes yes
Vector_Bounds: [1 ] data_in
Null_Allowed: no no
PORT_TABLE:
Port Name: address write_en
Description: "address input line(s)" "write enable line"
Direction: in in
Default_Type: d d
Allowed_Types: [d] [d]
Vector: yes no
Vector_Bounds: [1 ] 
Null_Allowed: no no
PORT_TABLE:
Port Name: select
Description: "chip select line(s)"
Direction: in
Default_Type: d
Allowed_Types: [d]
Vector: yes
Vector_Bounds: [1 16]
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: select_value
Description: "decimal active value for select line comparison"
Data_Type: int
Default_Value: 1
Limits: [0 32767]
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: ic
Description: "initial bit state @ dc"
Data_Type: int
Default_Value: 2
Limits: [0 2]
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: read_delay
Description: "read delay from address/select/write.en active"
Data_Type: real
Default_Value: 100.0e9
Limits: [1.0e12 ]
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: data_load address_load
Description: "data_in load value (F)" "addr. load value (F)"
Data_Type: real real
Default_Value: 1.0e12 1.0e12
Limits:  
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: select_load
Description: "select load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: enable_load
Description: "enable line load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
 Description:
The digital RAM is an Mwide, Ndeep random access memory element with programmable select lines, tristated data out lines, and a single write/~read line. The width of the RAM words (M) is set through the use of the word width parameter. The depth of the RAM (N) is set by the number of address lines input to the device. The value of N is related to the number of address input lines (P) by the following equation: [2^{P} = N]There is no reset line into the device. However, an initial value for all bits may be specified by setting the ic parameter to either 0 or 1. In reading a word from the ram, the read delay value is invoked, and output will not appear until that delay has been satisfied. Separate rise and fall delays are not supported for this device.
Note that UNKNOWN inputs on the address lines are not allowed during a write. In the event that an address line does indeed go unknown during a write, the entire contents of the ram will be set to unknown. This is in contrast to the data in lines being set to unknown during a write; in that case, only the selected word will be corrupted, and this is corrected once the data lines settle back to a known value. Note that protection is added to the write en line such that extended UNKNOWN values on that line are interpreted as ZERO values. This is the equivalent of a read operation and will not corrupt the contents of the RAM. A similar mechanism exists for the select lines. If they are unknown, then it is assumed that the chip is not selected.
Detailed timingchecking routines are not provided in this model, other than for the enable delay and select delay restrictions on read operations. You are advised, therefore, to carefully check the timing into and out of the RAM for correct read and write cycle times, setup and hold times, etc. for the particular device they are attempting to model.
Example SPICE Usage:
a4 [3 4 5 6] [3 4 5 6] [12 13 14 15 16 17 18 19] 30 [22 23 24] ram2
.model ram2 d_ram(select_value = 2 ic = 2 read_delay = 80e9)
Digital Source
NAME_TABLE:
C_Function_Name: cm_d_source
Spice_Model_Name: d_source
Description: "digital signal source"
PORT_TABLE:
Port Name: out
Description: "output"
Direction: out
Default_Type: d
Allowed_Types: [d]
Vector: yes
Vector_Bounds: 
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: input_file
Description: "digital input vector filename"
Data_Type: string
Default_Value: "source.txt"
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: input_load
Description: "input loading capacitance (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: no
 Description:
The digital source provides for straightforward descriptions of digital signal vectors in a tabular format. The model reads input from the input file and, at the times specified in the file, generates the inputs along with the strengths listed. The format of the input file is as shown below. Note that comment lines are delineated through the use of a single `*' character in the first column of a line. This is similar to the way the SPICE program handles comments.
* T c n n n . . .
* i l o o o . . .
* m o d d d . . .
* e c e e e . . .
* k a b c . . .
0.0000 Uu Uu Us Uu . . .
1.234e9 0s 1s 1s 0z . . .
1.376e9 0s 0s 1s 0z . . .
2.5e7 1s 0s 1s 0z . . .
2.5006e7 1s 1s 1s 0z . . .
5.0e7 0s 1s 1s 0z . . .
Note that in the example shown, whitespace (any combination of blanks, tabs, commas) is used to separate the time and state/strength tokens. The order of the input columns is important; the first column is always interpreted to mean `time'. The second through the N'th columns map to the out[0] through out[N2] output nodes. A noncommented line that does not contain enough tokens to completely define all outputs for the digital source will cause an error. Also, time values must increase monotonically or an error will result in reading the source file.
Errors will also occur if a line exists in source.txt that is neither a comment nor vector line. The only exception to this is in the case of a line that is completely blank; this is treated as a comment (note that such lines often occur at the end of text within a file; ignoring these in particular prevents nuisance errors on the part of the simulator).
Example SPICE Usage:
a3 [2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17] input_vector
.model input_vector d_source(input_file = "source_simple.text")
 Note:
The file named by the parameter filename in input_file="filename" is sought after according to a search list described in12.1.3.
LUT
NAME_TABLE:
C_Function_Name: cm_d_lut
Spice_Model_Name: d_lut
Description: "digital ninput lookup table gate"
PORT_TABLE:
Port_Name: in out
Description: "input" "output"
Direction: in out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: yes no
Vector_Bounds: [1 ] 
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: input_load
Description: "input load value (F)"
Data_Type: real
Default_Value: 1.0e12
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: table_values
Description: "lookup table values"
Data_Type: string
Default_Value: "0"
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: no
 Description:
The lookup table provides a way to map any arbitrary ninput, 1output combinational logic block to XSPICE. The inputs are mapped to the output using a string of length 2^n. The string may contain values "0", "1" or "X", corresponding to an output of low, high, or unknown, respectively. The outputs are only mapped for inputs which are valid logic levels. Any unknown bit in the input vector will always produce an unknown output. The first character of the string table_values corresponds to all inputs value zero, and the last (2^n) character corresponds to all inputs value one, with the first signal in the input vector being the least significant bit. For example, a 2input lookup table representing the function (A * B) (that is, A AND B), with input vector [A B] can be constructed with a table_values string of "0001"; function (~A * B) with input vector [A B] can be constructed with a table_values string of "0010". The delays associated with an output rise and those associated with an output fall may be specified independently. The model also posts an input load value (in farads) based on the parameter input_load. The output of this model does not respond to the total loading it sees on the output; it will always drive the output strongly with the specified delays.
Example SPICE Usage:
* LUT encoding 3bit parity function
a4 [1 2 3] 5 lut_pty3_1
.model lut_pty3_1 d_lut(table_values = "01101001"
+ input_load 2.0e12)
General LUT
NAME_TABLE:
C_Function_Name: cm_d_genlut
Spice_Model_Name: d_genlut
Description: "digital ninput x moutput lookup table gate"
PORT_TABLE:
Port_Name: in out
Description: "input" "output"
Direction: in out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: yes yes
Vector_Bounds:  
Null_Allowed: no no
PARAMETER_TABLE:
Parameter_Name: rise_delay fall_delay
Description: "rise delay" "fall delay"
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: yes yes
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: input_load input_delay
Description: "input load value (F)" "input delay"
Data_Type: real real
Default_Value: 1.0e12 0.0
Limits:  
Vector: yes yes
Vector_Bounds:  
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: table_values
Description: "lookup table values"
Data_Type: string
Default_Value: "0"
Limits: 
Vector: no
Vector_Bounds: 
Null_Allowed: no
 Description:
The lookup table provides a way to map any arbitrary ninput, moutput combinational logic block to XSPICE. The inputs are mapped to the output using a string of length m * (2^n). The string may contain values "0", "1", "X", or "Z", corresponding to an output of low, high, unknown, or highimpedance, respectively. The outputs are only mapped for inputs which are valid logic levels. Any unknown bit in the input vector will always produce an unknown output. The character string is in groups of (2^n) characters, one group corresponding to each output pin, in order. The first character of a group in the string table_values corresponds to all inputs value zero, and the last (2^n) character in the group corresponds to all inputs value one, with the first signal in the input vector being the least significant bit. For example, a 2input lookup table representing the function (A * B) (that is, A AND B), with input vector [A B] can be constructed with a table_values string of "0001"; function (~A * B) with input vector [A B] can be constructed with a "table_values" string of "0010". The delays associated with each output pin's rise and those associated with each output pin's fall may be specified independently. The model also posts independent input load values per input pin (in farads) based on the parameter input_load. The parameter input_delay provides a way to specify additional delay between each input pin and the output. This delay is added to the rise or falltime of the output. The output of this model does not respond to the total loading it sees on the output; it will always drive the output strongly with the specified delays.
Example SPICE Usage:
* LUT encoding 3bit parity function
a4 [1 2 3] [5] lut_pty3_1
.model lut_pty3_1 d_genlut(table_values = "01101001"
+ input_load [2.0e12])
* LUT encoding a tristate inverter function (en in out)
a2 [1 2] [3] lut_triinv_1
.model lut_triinv_1 d_genlut(table_values = "Z1Z0")
* LUT encoding a halfadder function (A B Carry Sum)
a8 [1 2] [3 4] lut_halfadd_1
.model lut_halfadd_1 d_genlut(table_values = "00010110"
+ rise_delay [ 1.5e9 1.0e9 ] fall_delay [ 1.5e9 1.0e9 ])
Predefined Node Types for event driven simulation
The following prewritten node types are included with the XSPICE simulator. These should provide you not only with valuable eventdriven modeling capabilities, but also with examples to use for guidance in creating new UDN (user defined node) types. You may access these node data by the plot (17.5.48) or eprint (17.5.25) commands.
Digital Node Type
The `digital' node type is directly built into the simulator. 12 digital node values are available. They are described by a two character string (the state/strength token). The first character (0, 1, or U) gives the state of the node (logic zero, logic one, or unknown logic state). The second character (s, r, z, u) gives the "strength" of the logic state (strong, resistive, hiimpedance, or undetermined). So these are the values we have: 0s, 1s, Us, 0r, 1r, Ur, 0z, 1z, Uz, 0u, 1u, Uu.
Real Node Type
The `real' node type provides for eventdriven simulation with doubleprecision floating point data. This type is useful for evaluating sampleddata filters and systems. The type implements all optional functions for UserDefined Nodes, including inversion and node resolution. For inversion, the sign of the value is reversed. For node resolution, the resultant value at a node is the sum of all values output to that node. The node is implemented as a user defined node in ngspice/src/xspice/icm/xtraevt/real.
Int Node Type
The `int' node type provides for eventdriven simulation with integer data. This type is useful for evaluating roundoff error effects in sampleddata systems. The type implements all optional functions for UserDefined Nodes, including inversion and node resolution. For inversion, the sign of the integer value is reversed. For node resolution, the resultant value at a node is the sum of all values output to that node. The node is implemented as a user defined node in ngspice/src/xspice/icm/xtraevt/int.
(Digital) Input/Output
The analog code models use the standard (analog) nodes provided by ngspice and thus are using all the commands for sourcing, storing, printing, and plotting data.
I/O for event nodes (digital, real, int, and UDNs) is offered by the following tools: For output you may use the plot (17.5.48) or eprint (17.5.25) commands, as well as edisplay (17.5.24) and eprvcd (17.5.26). The latter writes all node data to a VCD file (a digital standard interface) that may be analysed by viewers like gtkwave. For input, you may create a test bench with existing code models (oscillator (12.3.3), frequency divider (12.4.19), state machine (12.4.18) etc.). Reading data from a file is offered by d_source (12.4.21). Some comments and hints have been provided by Sdaau. You may also use the analog input from file, (filesource 12.2.8) and convert its analog input to the digital type by the adc_bridge (12.3.2). If you want reading data from a VCD file, please have a look at ngspice tips and examples forum and apply a python script provided by Sdaau to translate the VCD data to d_source or filesource input.
Verilog A Device models
Introduction
New compact device models today are released as VerilogA code. Ngspice applies ADMS to translate the va code into ngspice C syntax. Currently a limited number of VerilogA models is supported: HICUM level0 and level2 (HICUM model web page), MEXTRAM (MEXTRAM model web page), EKV (EKV model web page) and PSP (NXP PSP web site).
ADMS
ADMS is a code generator that converts electrical compact device models specified in highlevel description language into readytocompile C code for the API of spice simulators. Based on transformations specified in XML language, ADMS transforms VerilogAMS code into other target languages. Here we use it to to translate the va code into ngspice C syntax.
To make use of it, a set of ngspice specific XML files is distributed with ngspice in ngspice\src\spicelib\devices\adms\admst. Their translation is done by the code generator executable admsXml (see below).
How to integrate a VerilogA model into ngspice
How to setup a *.va model for ngspice
Unfortunately most of the above named models' licenses are not compatible to free software rules as defined by DFSG. Therefore since ngspice28 the va model files are no longer part of the standard ngspice distribution. They may however be downloaded as a 7z archive from the ngspice28 file distribution folder. After downloading, you may expand the zipped files into your ngspice top level folder. The models enable dc, ac, and tran simulations. Noise simulation is not supported.
Other (foreign) va model files will not compile without code tweaking, due to the limited capabilities of our ADMS installation.
Adding admsXml to your build environment
The actual admsXml code is maintained by the QUCS project and is available at GitHub.
Information on how to compile and install admsXml for Linux or Cygwin is available on the GitHub page. For MS Windows users admsXml.exe is available for download here. You may copy admsXml.exe to your MSYS2 setup into the folder msys64\mingw64\bin, if 64 bit compilation is intended.
More information, though partially outdated, is obtainable from the ngspice web pages.
Compile ngspice with ADMS
In the top level ngspice folder there are two compile scripts compile_min.sh and compile_linux.sh. They contain information how to compile ngspice with ADMS. You will have to run autogen.sh with the adms flag
./autogen.sh  adms
In addition you have to add  enableadms to the ./configure command. Please check 32.1 for perequisites and further details.
Compiling ngspice with ADMS with MS Visual Studio is not supported.
MixedLevel Simulation (ngspice with TCAD)
Cider
Ngspice implements mixedlevel simulation through the merging of its code with CIDER (details see Chapt. 30).
CIDER is a mixedlevel circuit and device simulator that provides a direct link between technology parameters and circuit performance. A mixedlevel circuit and device simulator can provide greater simulation accuracy than a standalone circuit or device simulator by numerically modeling the critical devices in a circuit. Compact models can be used for noncritical devices.
CIDER couples the latest version of SPICE3 (version 3F.2) [JOHN92] to a internal Cbased device simulator, DSIM. SPICE3 provides circuit analyses, compact models for semiconductor devices, and an interactive user interface. DSIM provides accurate, one and twodimensional numerical device models based on the solution of Poisson's equation, and the electron and hole currentcontinuity equations. DSIM incorporates many of the same basic physical models found in the the Stanford twodimensional device simulator PISCES [PINT85]. Input to CIDER consists of a SPICElike description of the circuit and its compact models, and PISCESlike descriptions of the structures of numerically modeled devices. As a result, CIDER should seem familiar to designers already accustomed to these two tools. For example, SPICE3F.2 input files should run without modification, producing identical results.
CIDER is based on the mixedlevel circuit and device simulator CODECS [MAYA88] and is a replacement for this program. The basic algorithms of the two programs are the same. Some of the differences between CIDER and CODECS are described below. The CIDER input format has greater flexibility and allows increased access to physical model parameters. New physical models have been added to allow simulation of stateoftheart devices. These include transverse field mobility degradation [GATE90] that is important in scaleddown MOSFETs and a polysilicon model for polyemitter bipolar transistors. Temperature dependence has been included for most physical models over the range from 50°C to 150°C. The numerical models can be used to simulate all the basic types of semiconductor devices: resistors, MOS capacitors, diodes, BJTs, JFETs and MOSFETs. BJTs and JFETs can be modeled with or without a substrate contact. Support has been added for the management of device internal states. Postprocessing of device states can be performed using the NUTMEG user interface of SPICE3. Previously computed states can be loaded into the program to provide accurate initial guesses for subsequent analyses. Finally, numerous small bugs have been discovered and fixed, and the program has been ported to a wider variety of computing platforms.
Berkeley tradition calls for the naming of new versions of programs by affixing a (number, letter, number) triplet to the end of the program name. Under this scheme, CIDER should instead be named CODECS2A.l. However, tradition has been broken in this case because major incompatibilities exist between the two programs and because it was observed that the acronym CODECS is already used in the analog design community to refer to coderdecoder circuits.
Details of the basic semiconductor equations and the physical models used by CIDER are not provided in this manual. Unfortunately, no other single source exists that describes all of the relevant background material. Comprehensive reviews of device simulation can be found in [PINT90] and the book [SELB84]. CODECS and its inversionlayer mobility model are described in [MAYA88] and LGATE90], respectively. PISCES and its models are described in [PINT85]. Temperature dependencies for the PISCES models used by CIDER are available in [SOLL90].
GSS, Genius
For Linux users the cooperation of the TCAD software GSS with ngspice might be of interest, see http://ngspice.sourceforge.net/gss.html. This project is no longer maintained however, but has moved into the Genius simulator, still available as open source cogenda genius.
Analyses and Output Control (batch mode)
The command lines described in this chapter are specifying analyses and outputs within the circuit description file. They start with a `.' (dot commands). Specifying analyses and plots (or tables) in the input file with dot commands is used with batch runs. Batch mode is entered when either the b option is given upon starting ngspice
ngspice b r rawfile.raw circuitfile.cir
or when the default input source is redirected from a file (see also Chapt. 16.4.1).
ngspice < circuitfile.cir
In batch mode, the analyses specified by the control lines in the input file (e.g. .ac, .tran, etc.) are immediately executed. If the r rawfile option is given then all data generated is written to a ngspice rawfile. The rawfile may later be read by the interactive mode of ngspice using the load command (see 17.5.40). In this case, the .save line (see 15.6) may be used to record the value of internal device variables (see Appendix, Chapt. 31).
If a rawfile is not specified, then output plots (in `lineprinter' form) and tables can be printed according to the .print, .plot, and .four control lines, described in Chapt. 15.6.
If ngspice is started in interactive mode (see Chapt. 16.4.2), like
ngspice circuitfile.cir
and no control section (.control ... .endc, see 16.4.3) is provided in the circuit file, the dot commands are not executed immediately, but are waiting for manually receiving the command run.
Simulator Variables (.options)
Various parameters of the simulations available in Ngspice can be altered to control the accuracy, speed, or default values for some devices. These parameters may be changed via the option command (described in Chapt. 17.5.47) or via the .options line:
General form:
.options opt1 opt2 ... (or opt=optval ...)
Examples:
.options reltol=.005 trtol=8
The options line allows the user to reset program control and user options for specific simulation purposes. Options specified to Ngspice via the option command (see Chapt. ) are also passed on as if specified on a .options line. Any combination of the following options may be included, in any order. `x' (below) represents some positive number.
General Options
 ACCT
causes accounting and run time statistics to be printed.  NOACCT
no printing of statistics, no printing of the Initial Transient Solution.  NOINIT
suppresses only printing of the Initial Transient Solution, maybe combined with ACCT.  LIST
causes the summary listing of the input data to be printed.  NOMOD
suppresses the printout of the model parameters.  NOPAGE
suppresses page ejects.  NODE
causes the printing of the node table.  OPTS
causes the option values to be printed.  SEED=valrandom
Sets the seed value of the random number generator. val may be any integer number greater than 0. As an alternative random will set the seed value to the time in seconds since 1.1.1970.  SEEDINFO
will print the seed value when it has been set to a new integer number.  TEMP=x
Resets the operating temperature of the circuit. The default value is 27 (C) (300K). TEMP can be overridden per device by a temperature specification on any temperature dependent instance. May also be generally overridden by a .TEMP card (2.11).  TNOM=x
resets the nominal temperature at which device parameters are measured. The default value is 27 (C) (300 deg K). TNOM can be overridden by a specification on any temperature dependent device model.  WARN=10
enables or turns of SOA (Safe Operating Area) voltage warning messages (default: 0).  MAXWARNS=x
specifies the maximum number of SOA (Safe Operating Area) warning messages per model (default: 5).  SAVECURRENTS
save currents through all terminals of the following devices: M, J, Q, D, R, C, L, B, F, G, W, S, I (see 2.1.2). Recommended only for small circuits, because otherwise memory requirements explode and simulation speed suffers. See 15.7 for more details.
DC Solution Options
The following options controls properties pertaining to DC analysis and algorithms. Since transient analysis is based on DC many of the options affect the latter one.
 ABSTOL=x
resets the absolute current error tolerance of the program. The default value is 1 pA.  GMIN=x
resets the value of GMIN, the minimum conductance allowed by the program. The default value is 1.0e12.  ITL1=x
resets the dc iteration limit. The default is 100.  ITL2=x
resets the dc transfer curve iteration limit. The default is 50.  KEEPOPINFO
Retain the operating point information when either an AC, Distortion, or PoleZero analysis is run. This is particularly useful if the circuit is large and you do not want to run a (redundant) .OP analysis.  NOOPITER
Go directly to gmin stepping, skipping the first iteration.  PIVREL=x
resets the relative ratio between the largest column entry and an acceptable pivot value. The default value is 1.0e3. In the numerical pivoting algorithm the allowed minimum pivot value is determined by (\mathtt{EPSREL} = \mathtt{AMAX1}\left( {\mathtt{PIVREL} \cdot \mathtt{MAXVAL},\mathtt{PIVTOL}} \right)) where MAXVAL is the maximum element in the column where a pivot is sought (partial pivoting).  PIVTOL=x
resets the absolute minimum value for a matrix entry to be accepted as a pivot. The default value is 1.0e13.  RELTOL=x
resets the relative error tolerance of the program. The default value is 0.001 (0.1%).  RSHUNT=x
introduces a resistor from each analog node to ground. The value of the resistor should be high enough to not interfere with circuit operations. The XSPICE option has to be enabled (see 32.1.7) .  VNTOL=x
resets the absolute voltage error tolerance of the program. The default value is 1 (\mu V).
Matrix Conditioning info
In SPICEbased simulators, specific problems arise with certain circuit topologies. One issue is the absence of a DC path to ground at some node. This may happen when two capacitors are connected in series with no other connection at the common node, or when code models are cascaded. The result is an illconditioned or nearly singular matrix that prevents the simulation from completing. Configuring with XSPICE introduces the rshunt option to help eliminate this problem. The option inserts resistors to ground at all the analog nodes in the circuit. In general, the value of rshunt is set to some high resistance (e.g. (1000\mathsf{M}\Omega) or greater) so that the operation of the circuit is essentially unaffected but the matrix problems are corrected. If a `no DC path to ground' or a `matrix is nearly singular' error message is encountered, add the following .option card to the circuit deck:
.option rshunt = 1.0e12
Usually a value of (1\mathsf{ T}\Omega) is sufficient to correct the problem. In bad cases one can try lowering the value to (10\mathsf{ G}\Omega) or even (1\mathsf{G}\Omega).
A different matrix conditioning problem occurs if an inductor is placed in parallel to a voltage source. The AC simulation will fail, because it is preceded by an OP analysis. Option NOOPAC (15.1.3) will help if the circuit is linear. However, if the circuit is nonlinear the OP analysis is essential. In such a case, adding a small resistor (e.g. (0.1\mathsf{m}\Omega)) in series to the inductor will help to obtain convergence.
.option rseries = 1.0e4
adds a series resistor to each inductor in the circuit. Be careful when using behavioral inductors (see 3.2.12), as the result may become unpredictable.
AC Solution Options
 NOOPAC
Do not run an operating point (OP) analysis prior to an AC analysis. This option requires that the circuit is linear, i.e. consists only of R, L, and C devices, independent V, I sources and linear dependent E, G, H, and F sources (without poly statement, nonbehavioral). If a nonlinear device is detected, the OP analysis is executed automatically. This option is of interest e.g. in nested LC circuits where no series resistance for L devices is present. During the OP analysis an illformed matrix may be encountered, causing the simulator to abort with an error message.
Transient Analysis Options
 AUTOSTOP
stops a transient analysis after successfully calculating all functions (15.4) specified with the dot command .meas. Autostop is not available with the meas (17.5.42) command used in control mode.  CHGTOL=x
resets the charge tolerance of the program. The default value is 1.0e14.  CONVSTEP=x
relative step limit applied to code models.  CONVABSSTEP=x
absolute step limit applied to code models.  GMINSTEPS=x
[*] sets the number of Gmin steps to be attempted. If the value is set to zero, the standard gmin stepping algorithm is skipped. The standard behavior is that gmin stepping is tried before going to the source stepping algorithm.  INTERP
interpolates output data onto fixed time steps on a TSTEP grid (15.3.9). Uses linear interpolation between previous and next time values. Simulation itself is not influenced by this option. This option can be used in all simulation modes (batch, control or interactive, 16.4). It may drastically reduce memory requirements in control mode, and file size in batch mode, but care is needed not to undersample the output data. See also the command linearize (17.5.38) that achieves a similar result by postprocessing the data in control mode. The Ngspice/examples/xspice/deltasigma/deltasigma1.cir example demonstrates how INTERP reduces memory requirements and speeds up plotting.  ITL3=x
resets the lower transient analysis iteration limit. The default value is 4. (Note: not implemented in Spice3).  ITL4=x
resets the transient analysis timepoint iteration limit. The default is 10.  ITL5=x
resets the transient analysis total iteration limit. The default is Set ITL5=0 to omit this test. (Note: not implemented in Spice3).
 ITL6=x
[*] synonym for SRCSTEPS.  MAXEVITER=x
sets the maximum number of event iterations per analysis point.  MAXOPALTER=x
specifies the maximum number of analog/event alternations that the simulator will use to solve a hybrid circuit.  MAXORD=x
[*] specifies the maximum order for the numerical integration method used by SPICE. Possible values for the Gear method are from 2 (the default) to 6. Using the value 1 with the trapezoidal method specifies backward Euler integration.  METHOD=name
sets the numerical integration method used by SPICE. Possible names are `Gear' or `trapezoidal' (or just `trap'). The default is trapezoidal.  NOOPALTER=TRUEFALSE
if set to false, alternations between analog/event are enabled.  RAMPTIME=x
During source stepping, this option sets the rate of change of independent supplies. It also affects code model inductors and capacitors that have initial conditions specified.  SRCSTEPS=x
[*] a nonzero value causes SPICE to use a sourcestepping method to find the DC operating point. The value specifies the number of steps.  TRTOL=x
resets the transient error tolerance. The default value is 7. This parameter is an estimate of the factor by which SPICE overestimates the actual truncation error. If XSPICE is configured and 'A' devices are included, the value is internally set to 1 for higher precision. This slows down transient analysis with a factor of two.  XMU=x
sets the damping factor for trapezoidal integration. The default value is XMU=0.5. A value < 0.5 may be chosen. Even a small reduction, e.g. to 0.495, may already suppress trap ringing. The reduction has to be set carefully in order not to excessively damp circuits that are prone to ringing or oscillation, which might lead the user to believe that the circuit is stable.
ELEMENT Specific options
 BADMOS3
Use the older version of the MOS3 model with the `kappa' discontinuity.  DEFAD=x
resets the value for MOS drain diffusion area; the default is 0.  DEFAS=x
resets the value for MOS source diffusion area; the default is 0.  DEFL=x
resets the value for MOS channel length; the default is 100 (\mu m).  DEFW=x
resets the value for MOS channel width; the default is 100 (\mu m).  SCALE=x
set the element scaling factor for geometric element parameters whose default unit is meters. As an example: scale=1u and a MOSFET instance parameter W=10 will result in a width of 10(\mu m) for this device. An area parameter AD=20 will result in (\mathsf{20e  12 m^{2}}). Following instance parameters are scaled:
 Resistors and Capacitors: W, L
 Diodes: W, L, Area
 JFET, MESFET: W, L, Area
 MOSFET: W, L, AS, AD, PS, PD, SA, SB, SC, SD
Transmission Lines Specific Options
 TRYTOCOMPACT
Applicable only to the LTRA model (see 6.2.1). When specified, the simulator tries to condense an LTRA transmission line's past history of input voltages and currents.
Precedence of option and .options commands
There are various ways to set the above mentioned options in Ngspice. If no option or .options lines are set by the user, internal default values are given for each of the simulator variables.
You may set options in the init files spinit or .spiceinit via the option command (see Chapt. 17.5.47). The values given there will supersede the default values. If you set options via the .options line in your input file, their values will supersede the default and init file data. Finally, if you set options inside a .control ... .endc section, these values will again supersede any simulator variables given so far.
Initial Conditions
.NODESET: Specify Initial Node Voltage Guesses
General form:
.nodeset v(nodnum)=val v(nodnum)=val ...
.nodeset all=val
Examples:
.nodeset v(12)=4.5 v(4)=2.23
.nodeset all=1.5
The .nodeset line helps the program find the DC or initial transient solution by making a preliminary pass with the specified nodes held to the given voltages. The restrictions are then released and the iteration continues to the true solution. The .nodeset line may be necessary for convergence on bistable or astable circuits. .nodeset all=val allows to set all starting node voltages (except for the ground node) to the same value. In general, the .nodeset line should not be necessary.
.IC: Set Initial Conditions
General form:
.ic v(nodnum)=val v(nodnum)=val ...
Examples:
.ic v(11)=5 v(4)=5 v(2)=2.2
The .ic line is for setting transient initial conditions. It has two different interpretations, depending on whether the uic parameter is specified on the .tran control line, or not. One should not confuse this line with the .nodeset line. The .nodeset line is only to help DC convergence, and does not affect the final bias solution (except for multistable circuits). The two indicated interpretations of this line are as follows:
 When the uic parameter is specified on the .tran line, the node voltages specified on the .ic control line are used to compute the capacitor, diode, BJT, JFET, and MOSFET initial conditions. This is equivalent to specifying the ic=... parameter on each device line, but is much more convenient. The ic=... parameter can still be specified and takes precedence over the .ic values. Since no dc bias (initial transient) solution is computed before the transient analysis, one should take care to specify all dc source voltages on the .ic control line if they are to be used to compute device initial conditions.
 When the uic parameter is not specified on the .tran control line, the DC bias (initial transient) solution is computed before the transient analysis. In this case, the node voltages specified on the .ic control lines are forced to the desired initial values during the bias solution. During transient analysis, the constraint on these node voltages is removed. This is the preferred method since it allows Ngspice to compute a consistent dc solution.
Analyses
.AC: SmallSignal AC Analysis
General form:
.ac dec nd fstart fstop
.ac oct no fstart fstop
.ac lin np fstart fstop
Examples:
.ac dec 10 1 10K
.ac dec 10 1K 100MEG
.ac lin 100 1 100HZ
dec stands for decade variation, and nd is the number of points per decade. oct stands for octave variation, and no is the number of points per octave. lin stands for linear variation, and np is the number of points. fstart is the starting frequency, and fstop is the final frequency. If this line is included in the input file, Ngspice performs an AC analysis of the circuit over the specified frequency range. Note that in order for this analysis to be meaningful, at least one independent source must have been specified with an ac value. Typically it does not make much sense to specify more than one ac source. If you do, the result will be a superposition of all sources and difficult to interpret.
Example:
Basic RC circuit
r 1 2 1.0
c 2 0 1.0
vin 1 0 dc 0 ac 1 $ < the ac source
.options noacct
.ac dec 10 .01 10
.plot ac vdb(2) xlog
.end
In this AC (or 'small signal') analysis all nonlinear devices are linearized around their actual DC operating point. All L and C devices get their imaginary value that depends on the actual frequency step. Each output vector will be calculated relative to the input voltage (current) given by the AC value ((V_{in}) equals 1 in the example above). The resulting node voltages (and branch currents) are complex vectors. Therefore one has to be careful using the plot command, specifically, one may use the variants of vxx(node) described in Chapt. 15.6.2 like vdb(2) (see also the above example).
.DC: DC Transfer Function
General form:
.dc srcnam vstart vstop vincr [src2 start2 stop2 incr2]
Examples:
.dc VIN 0.25 5.0 0.25
.dc VDS 0 10 .5 VGS 0 5 1
.dc VCE 0 10 .25 IB 0 10u 1u
.dc RLoad 1k 2k 100
.dc TEMP 15 75 5
The .dc line defines the dc transfer curve source and sweep limits (with capacitors open and inductors shorted). srcnam is the name of an independent voltage or current source, a resistor, or the circuit temperature. vstart, vstop, and vincr are the starting, final, and incrementing values, respectively. The first example causes the value of the voltage source (V_{IN}) to be swept from 0.25 Volts to 5.0 Volts with steps of 0.25 Volt. A second source (src2) may optionally be specified with its own associated sweep parameters. In such a case the first source is swept over its own range for each value of the second source. This option is useful for obtaining semiconductor device output characteristics. See the example on transistor characterization (21.3).
.DISTO: Distortion Analysis
General form:
.disto dec nd fstart fstop <f2overf1>
.disto oct no fstart fstop <f2overf1>
.disto lin np fstart fstop <f2overf1>
Examples:
.disto dec 10 1kHz 100MEG
.disto dec 10 1kHz 100MEG 0.9
The .disto line does a smallsignal distortion analysis of the circuit. A multidimensional Volterra series analysis is done using multidimensional Taylor series to represent the nonlinearities at the operating point. Terms of up to third order are used in the series expansions.
If the optional parameter f2overf1 is not specified, .disto does a harmonic analysis  i.e., it analyses distortion in the circuit using only a single input frequency (F_{1}), which is swept as specified by arguments of the .disto command exactly as in the .ac command. Inputs at this frequency may be present at more than one input source, and their magnitudes and phases are specified by the arguments of the distof1 keyword in the input file lines for the input sources (see the description for independent sources). (The arguments of the distof2 keyword are not relevant in this case).
The analysis produces information about the AC values of all node voltages and branch currents at the harmonic frequencies (2F_{1}) and , vs. the input frequency (F_{1}) as it is swept. (A value of 1 (as a complex distortion output) signifies (\cos\left( {2\pi\left( {2F_{1}} \right)t} \right)) at (2F_{1}) and (\cos\left( {2\pi\left( {3F_{1}} \right)t} \right)) at (3F_{1}), using the convention that 1 at the input fundamental frequency is equivalent to (\cos\left( {2\pi F_{1}t} \right)).) The distortion component desired ((2F_{1}) or (3F_{1})) can be selected using commands in ngnutmeg, and then printed or plotted. (Normally, one is interested primarily in the magnitude of the harmonic components, so the magnitude of the AC distortion value is looked at). It should be noted that these are the AC values of the actual harmonic components, and are not equal to HD2 and HD3. To obtain HD2 and HD3, one must divide by the corresponding AC values at (F_{1}), obtained from an .ac line. This division can be done using ngnutmeg commands.
If the optional f2overf1 parameter is specified, it should be a real number between (and not equal to) 0.0 and 1.0; in this case, .disto does a spectral analysis. It considers the circuit with sinusoidal inputs at two different frequencies (F_{1}) and (F_{2}). (F_{1}) is swept according to the .disto control line options exactly as in the .ac control line. (F_{2}) is kept fixed at a single frequency as (F_{1}) sweeps  the value at which it is kept fixed is equal to f2overf1 times fstart. Each independent source in the circuit may potentially have two (superimposed) sinusoidal inputs for distortion, at the frequencies (F_{1}) and (F_{2}). The magnitude and phase of the (F_{1}) component are specified by the arguments of the distof1 keyword in the source's input line (see the description of independent sources); the magnitude and phase of the (F_{2}) component are specified by the arguments of the distof2 keyword. The analysis produces plots of all node voltages/branch currents at the intermodulation product frequencies (F_{1} + F_{2}), (F_{1}  F_{2}), and (\left( {2F_{1}} \right)  F_{2}), vs the swept frequency (F_{1}). The IM product of interest may be selected using the setplot command, and displayed with the print and plot commands. It is to be noted as in the harmonic analysis case, the results are the actual AC voltages and currents at the intermodulation frequencies, and need to be normalized with respect to .ac values to obtain the IM parameters.
If the distof1 or distof2 keywords are missing from the description of an independent source, then that source is assumed to have no input at the corresponding frequency. The default values of the magnitude and phase are 1.0 and 0.0 respectively. The phase should be specified in degrees.
It should be carefully noted that the number f2overf1 should ideally be an irrational number, and that since this is not possible in practice, efforts should be made to keep the denominator in its fractional representation as large as possible, certainly above 3, for accurate results (i.e., if f2overf1 is represented as a fraction (\frac{A}{B}), where (A) and (B) are integers with no common factors, (B) should be as large as possible; note that (A < B) because f2overf1 is constrained to be (< 1)). To illustrate why, consider the cases where f2overf1 is 49/100 and 1/2. In a spectral analysis, the outputs produced are at (F_{1} + F_{2}), (F_{1}  F_{2}) and (2F_{1}  F_{2}). In the latter case, (F_{1}  F_{2} = F_{2}), so the result at the (F_{1}  F_{2}) component is erroneous because there is the strong fundamental (F_{2}) component at the same frequency. Also, (F_{1} + F_{2} = 2F_{1}  F_{2}) in the latter case, and each result is erroneous individually. This problem is not there in the case where f2overf1 = 49/100, because (F_{1}  F_{2} = 51/100) (F_{1} < > 49/100) (F_{1} = F_{2}). In this case, there are two very closely spaced frequency components at (F_{2}) and (F_{1}  F_{2}). One of the advantages of the Volterra series technique is that it computes distortions at mix frequencies expressed symbolically (i.e. (nF_{1} + mF_{2})), therefore one is able to obtain the strengths of distortion components accurately even if the separation between them is very small, as opposed to transient analysis for example. The disadvantage is of course that if two of the mix frequencies coincide, the results are not merged together and presented (though this could presumably be done as a postprocessing step). Currently, the interested user should keep track of the mix frequencies himself or herself and add the distortions at coinciding mix frequencies together should it be necessary.
Only a subset of the ngspice nonlinear device models supports distortion analysis. These are
 Diodes (DIO),
 BJT,
 JFET (level 1),
 MOSFETs (levels 1, 2, 3, 9, and BSIM1),
 MESFET (level 1).
.NOISE: Noise Analysis
General form:
.noise v(output <,ref>) src ( dec  lin  oct ) pts fstart fstop
+ <pts_per_summary>
Examples:
.noise v(5) VIN dec 10 1kHz 100MEG
.noise v(5,3) V1 oct 8 1.0 1.0e6 1
The .noise line does a noise analysis of the circuit. output is the node at which the total output noise is desired; if ref is specified, then the noise voltage v(output)  v(ref) is calculated. By default, ref is assumed to be ground. src is the name of an independent source to which input noise is referred. pts, fstart and fstop are .ac type parameters that specify the frequency range over which plots are desired. pts_per_summary is an optional integer; if specified, the noise contributions of each noise generator is produced every pts_per_summary frequency points. The .noise control line produces two plots, which can selected by setplot command:
 one for the Voltage or Current Noise Spectral Density (in
(\frac{V}{\sqrt{Hz}}) or (\frac{A}{\sqrt{Hz}}) respective the
input is a voltage or current source) curves (e.g. after setplot
noise1). There are two vectors over frequency:
 onoise_spectrum: This is the output noise voltage or current divided by (\sqrt{Hz}).
 inoise_spectrum: This the equivalent input noise = output noise divided by the gain of the circuit.
 one for the Total Integrated Noise (in (V) or (A)) over the
specified frequency range (e.g. after setplot noise2). There are two
vectors which are in reality scalars:
 onoise_total: This is the output noise voltage over the specified frequency range
 inoise_total: This the equivalent input noise over the specified frequency range = output noise divided by the gain of the circuit.
The units of all result vectors can be changed by using control variable sqrnoise:
 set sqrnoise: will deliver results in squared form, means the unit is (\frac{V^{2}}{Hz}) or (\frac{A^{2}}{Hz}) . This value refers more to the convinient Power Spectral Density.
Default setting of ngspice is unset sqrnoise, which delivers Voltage or Current Noise Spectral Density. This is more practical from designers point of view.
.OP: Operating Point Analysis
General form:
.op
The inclusion of this line in an input file directs ngspice to determine the dc operating point of the circuit with inductors shorted and capacitors opened.
Note: a DC analysis is automatically performed prior to a transient analysis to determine the transient initial conditions, and prior to an AC smallsignal, Noise, and PoleZero analysis to determine the linearized, smallsignal models for nonlinear devices (see the KEEPOPINFO variable 15.1.2).
.PZ: PoleZero Analysis
General form:
.pz node1 node2 node3 node4 cur pol
.pz node1 node2 node3 node4 cur zer
.pz node1 node2 node3 node4 cur pz
.pz node1 node2 node3 node4 vol pol
.pz node1 node2 NODE3 node4 vol zer
.pz node1 node2 node3 node4 vol pz
Examples:
.pz 1 0 3 0 cur pol
.pz 2 3 5 0 vol zer
.pz 4 1 4 1 cur pz
cur stands for a transfer function of the type (output voltage)/(input current) while vol stands for a transfer function of the type (output voltage)/(input voltage). pol stands for pole analysis only, zer for zero analysis only and pz for both. This feature is provided mainly because if there is a nonconvergence in finding poles or zeros, then, at least the other can be found. Finally, node1 and node2 are the two input nodes and node3 and node4 are the two output nodes. Thus, there is complete freedom regarding the output and input ports and the type of transfer function.
In interactive mode, the command syntax is the same except that the first field is pz instead of .pz. To print the results, one should use the command print all.
.SENS: DC or SmallSignal AC Sensitivity Analysis
General form:
.SENS OUTVAR
.SENS OUTVAR AC DEC ND FSTART FSTOP
.SENS OUTVAR AC OCT NO FSTART FSTOP
.SENS OUTVAR AC LIN NP FSTART FSTOP
Examples:
.SENS V(1,OUT)
.SENS V(OUT) AC DEC 10 100 100k
.SENS I(VTEST)
The sensitivity of OUTVAR to all nonzero device parameters is calculated when the SENS analysis is specified. OUTVAR is a circuit variable (node voltage or voltagesource branch current). The first form calculates sensitivity of the DC operatingpoint value of OUTVAR. The second form calculates sensitivity of the AC values of OUTVAR. The parameters listed for AC sensitivity are the same as in an AC analysis (see .AC above). The output values are in dimensions of change in output per unit change of input (as opposed to percent change in output or per percent change of input).
.TF: Transfer Function Analysis
General form:
.tf outvar insrc
Examples:
.tf v(5, 3) VIN
.tf i(VLOAD) VIN
The .tf line defines the smallsignal output and input for the dc smallsignal analysis. outvar is the small signal output variable and insrc is the smallsignal input source. If this line is included, ngspice computes the dc smallsignal value of the transfer function (output/input), input resistance, and output resistance. For the first example, ngspice would compute the ratio of V(5, 3) to VIN, the smallsignal input resistance at VIN, and the small signal output resistance measured across nodes 5 and 3.
.TRAN: Transient Analysis
General form:
.tran tstep tstop <tstart <tmax>> <uic>
Examples:
.tran 1ns 100ns
.tran 1ns 1000ns 500ns
.tran 10ns 1us
tstep is the printing or plotting increment for lineprinter output. For use with the postprocessor, tstep is the suggested computing increment. tstop is the final time, and tstart is the initial time. If tstart is omitted, it is assumed to be zero. The transient analysis always begins at time zero. In the interval <zero, tstart>, the circuit is analyzed (to reach a steady state), but no outputs are stored. In the interval <tstart, tstop>, the circuit is analyzed and outputs are stored. tmax is the maximum stepsize that ngspice uses; for default, the program chooses either tstep or (tstoptstart)/50.0, whichever is smaller. tmax is useful when one wishes to guarantee a computing interval that is smaller than the printer increment, tstep.
An initial transient operating point at time zero is calculated according to the following procedure: all independent voltages and currents are applied with their time zero values, all capacitances are opened, inductances are shorted, the non linear device equations are solved iteratively.
uic (use initial conditions) is an optional keyword that indicates that the user does not want ngspice to solve for the quiescent operating point before beginning the transient analysis. If this keyword is specified, ngspice uses the values specified using IC=... on the various elements as the initial transient condition and proceeds with the analysis. If the .ic control line has been specified (see 15.2.2), then the node voltages on the .ic line are used to compute the initial conditions for the devices. IC=... will take precedence over the values given in the .ic control line. If neither IC=... nor the .ic control line is given for a specific node, node voltage zero is assumed.
Look at the description on the .ic control line (15.2.2) for its interpretation when uic is not specified.
Transient noise analysis (at low frequency)
In contrast to the analysis types described above the transient noise simulation (noise current or voltage versus time) is not implemented as a dot command, but is integrated with the independent voltage source vsrc (isrc not yet available) (see 4.1.7) and used in combination with the .tran transient analysis (15.3.9).
Transient noise analysis deals with noise currents or voltages added to your circuits as a time dependent signal of randomly generated voltage excursion on top of a fixed dc voltage. The sequence of voltage values has random amplitude, but equidistant time intervals, selectable by the user (parameter NT). The resulting voltage waveform is differentiable and thus does not require any modifications of the matrix solving algorithms.
White noise is generated by the ngspice random number generator, applying the BoxMuller transform. Values are generated on the fly, each time when a breakpoint is hit.
The 1/f noise is generated with an algorithm provided by N. J. Kasdin (`Discrete simulation of colored noise and stochastic processes and (1/f^{a}) power law noise generation', Proceedings of the IEEE, Volume 83, Issue 5, May 1995 Page(s):802–827). The noise sequence (one for each voltage/current source with 1/f selected) is generated upon start up of the simulator and stored for later use. The number of points is determined by the total simulation time divided by NT, rounded up the the nearest power of 2. Each time a breakpoint ((n\bigstar NT), relevant to the noise signal) is hit, the next value is retrieved from the sequence.
If you want a random, but reproducible sequence, you may select a seed value for the random number generator by adding
setseed nn
to the spinit or .spiceinit file, nn being a positive integer number.
The transient noise analysis will allow the simulation of the three most important noise sources. Thermal noise is described by the Gaussian white noise. Flicker noise (pink noise or 1 over f noise) with an exponent between 0 and 2 is provided as well. Shot noise is dependent on the current flowing through a device and may be simulated by applying a nonlinear source as demonstrated in the following example:
Example:
* Shot noise test with B source, diode
* voltage on device (diode, forward)
Vdev out 0 DC 0 PULSE(0.4 0.45 10u)
* diode, forward direction, to be modeled with noise
D1 mess 0 DMOD
.model DMOD D IS=1e14 N=1
X1 0 mess out ishot
* device between 1 and 2
* new output terminals of device including noise: 1 and 3
.subckt ishot 1 2 3
* white noise source with rms 1V
* 20000 sample points
VNG 0 11 DC 0 TRNOISE(1 1n 0 0)
*measure the current i(v1)
V1 2 3 DC 0
* calculate the shot noise
* sqrt(2*current*q*bandwidth)
BI 1 3 I=sqrt(2*abs(i(v1))*1.6e19*1e7)*v(11)
.ends ishot
.tran 1n 20u
.control
run
plot (1)*i(vdev)
.endc
.end
The selection of the delta time step (NT) is worth discussing. Gaussian white noise has unlimited bandwidth and thus unlimited energy content. This is unrealistic. The bandwidth of real noise is limited, but it is still called `White' if it is the same level throughout the frequency range of interest, e.g. the bandwidth of your system. Thus you may select NT to be a factor of 10 smaller than the frequency limit of your circuit. A thorough analysis is still needed to clarify the appropriate factor. The transient method is probably most suited to circuits including switches, which are not amenable to the small signal .NOISE analysis (Chapt. 15.3.4).
There is a price you have to pay for transient noise analysis: the number of required time steps, and thus the simulation time, increases.
In addition to white and 1/f noise the independent voltage and current sources offer a random telegraph signal (RTS) noise source, also known as burst noise or popcorn noise, again for transient analysis. For each voltage (current) source offering RTS noise an individual noise amplitude is required for input, as well as a mean capture time and a mean emission time. The amplitude resembles the influence of a single trap on the current or voltage. The capture and emission times emulate the filling and emptying of the trap, typically following a Poisson process. They are generated from an random exponential distribution with respective mean values given by the user. To simulate an ensemble of traps, you may combine several current or voltage sources with different parameters.
All three sources (white, 1/f, and RTS) may be combined in a single command line.
RTS noise example:
* white noise, 1/f noise, RTS noise
* voltage source
VRTS2 13 12 DC 0 trnoise(0 0 0 0 5m 18u 30u)
VRTS3 11 0 DC 0 trnoise(0 0 0 0 10m 20u 40u)
VALL 12 11 DC 0 trnoise(1m 1u 1.0 0.1m 15m 22u 50u)
VW1of 21 0 DC trnoise(1m 1u 1.0 0.1m)
* current source
IRTS2 10 0 DC 0 trnoise(0 0 0 0 5m 18u 30u)
IRTS3 10 0 DC 0 trnoise(0 0 0 0 10m 20u 40u)
IALL 10 0 DC 0 trnoise(1m 1u 1.0 0.1m 15m 22u 50u)
R10 10 0 1
IW1of 9 0 DC trnoise(1m 1u 1.0 0.1m)
Rall 9 0 1
* sample points
.tran 1u 500u
.control
run
plot v(13) v(21)
plot v(10) v(9)
.endc
.end
Some details on RTS noise modeling are available in a recent article [20], available here.
This transient noise feature is still experimental.
The following questions (among others) are to be solved:
 clarify the theoretical background
 noise limit of plain ngspice (numerical solver, fft etc.)
 time step (NT) selection
 calibration of noise spectral density
 how to generate noise from a transistor model
 application benefits and limits
.PSS: Periodic Steady State Analysis
Experimental code, not yet made publicly available.
General form:
.pss gfreq tstab oscnob psspoints harms sciter steadycoeff <uic>
Examples:
.pss 150 200e3 2 1024 11 50 5e3 uic
.pss 624e6 1u v_plus 1024 10 150 5e3 uic
.pss 624e6 500n bout 1024 10 100 5e3 uic
gfreq is guessed frequency of fundamental suggested by user. When performing transient analysis the PSS algorithm tries to infer a new rough guess rgfreq on the fundamental. If gfreq is out of (\pm)10% with respect to rgfreq then gfreq is discarded.
tstab is stabilization time before the shooting begin to search for the PSS. It has to be noticed that this parameter heavily influence the possibility to reach the PSS. Thus is a good practice to ensure a circuit to have a right tstab, e.g. performing a separate TRAN analysis before to run PSS analysis.
oscnob is the node or branch where the oscillation dynamic is expected. PSS analysis will give a brief report of harmonic content at this node or branch.
psspoints is number of step in evaluating predicted period after convergence is reached. It is useful only in Time Domain plots. However this number should be higher than 2 times the requested harms. Otherwise the PSS analysis will properly adjust it.
harms number of harmonics to be calculated as requested by the user.
sciter number of allowed shooting cycle iterations. Default is 50.
steady_coeff is the weighting coefficient for calculating the Global Convergence Error (GCE), which is the reference value in order to infer is convergence is reached. The lower steady_coeff is set, the higher the accuracy of predicted frequency can be reached but at longer analysis time and sciter number. Default is 1e3.
uic (use initial conditions) is an optional keyword that indicates that the user does not want ngspice to solve for the quiescent operating point before beginning the transient analysis. If this keyword is specified, ngspice uses the values specified using IC=... on the various elements as the initial transient condition and proceeds with the analysis. If the .ic control line has been specified, then the node voltages on the .ic line are used to compute the initial conditions for the devices. Look at the description on the .ic control line for its interpretation when uic is not specified.
Measurements after AC, DC and Transient Analysis
.meas(ure)
The .meas or .measure statement (and its equivalent meas command, see Chapt. 17.5.42) are used to analyze the output data of a tran, ac, or dc simulation. The command is executed immediately after the simulation has finished.
batch versus interactive mode
.meas analysis may not be used in batch mode (b command line option), if an output file (rawfile) is given at the same time (r rawfile command line option). In this batch mode ngspice will write its simulation output data directly to the output file. The data is not kept in memory, thus is no longer available for further analysis. This is made to allow a very large output stream with only a relatively small memory usage. For .meas to be active you need to run the batch mode with a .plot or .print command. A better alternative may be to start ngspice in interactive mode.
If you need batch like operation, you may add a .control ... .endc section to the input file:
Example:
*input file
...
.tran 1ns 1000ns
...
*********************************
.control
run
write outputfile data
.endc
*********************************
.end
and start ngspice in interactive mode, e.g. by running the command
ngspice inputfile .
.meas<ure> then prints its userdefined data analysis to the standard output. The analysis includes propagation, delay, rise time, fall time, peaktopeak voltage, minimum or maximum voltage, the integral or derivative over a specified period and several other user defined values.
General remarks
The measure type {DCACTRANSP} depends on the data that is to be evaluated, either originating from a dc analysis, an ac analysis, or a transient simulation. The type SP to analyze a spectrum from the spec or fft commands is only available when executed in a meas command, see 17.5.42.
result will be a vector containing the result of the measurement. trig_variable, targ_variable, and out_variable are vectors stemming from the simulation, e.g. a voltage vector v(out).
VAL**=**val expects a real number val. It may be as well a parameter delimited by '' or {} expanding to a real number.
TD**=td and AT=**time expect a time value if measure type is tran. For ac and sp AT will be a frequency value, TD is ignored. For dc analysis AT is a voltage (or current), TD is ignored as well.
CROSS**=#** requires an integer number #. CROSS**=**LAST is possible as well. The same is expected by RISE and FALL.
Frequency and time values may start at 0 and extend to positive real numbers. Voltage (or current) inputs for the independent (scale) axis in a dc analysis may start or end at arbitrary real valued numbers.
Please note that not all of the .measure commands have been implemented.
Input
In the following lines you will get some explanation on the .measure commands. A simple simulation file with two sines of different frequencies may serve as an example. The transient simulation delivers time as the independent variable and two voltages as output (dependent variables).
Input file:
File: simplemeastran.sp
* Simple .measure examples
* transient simulation of two sine
* signals with different frequencies
vac1 1 0 DC 0 sin(0 1 1k 0 0)
vac2 2 0 DC 0 sin(0 1.2 0.9k 0 0)
.tran 10u 5m
*
.measure tran ... $ for the different inputs see below!
*
.control
run
plot v(1) v(2)
.endc
.end
After displaying the general syntax of the .measure statement, some examples are posted, referring to the input file given above.
Trig Targ
.measure according to general form 1 measures the difference in dc voltage, frequency or time between two points selected from one or two output vectors. The current examples all are using transient simulation. Measurements for tran analysis start after a delay time td. If you run other examples with ac simulation or spectrum analysis, time may be replaced by frequency, after a dc simulation the independent variable may become a voltage or current.
General form 1:
.MEASURE {DCACTRANSP} result TRIG trig_variable VAL=val
+ <TD=td> <CROSS=#  CROSS=LAST> <RISE=#  RISE=LAST>
+ <FALL=#  FALL=LAST> <TRIG AT=time> TARG targ_variable
+ VAL=val <TD=td> <CROSS=#  CROSS=LAST> <RISE=# 
+ RISE=LAST> <FALL=#  FALL=LAST> <TARG AT=time>
Measure statement example (for use in the input file given above):
.measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=2
measures the time difference between v(1) reaching 0.5 V for the first time on its first rising slope (TRIG) versus reaching 0.5 V again on its second rising slope (TARG), i.e. it measures the signal period.
Output:
tdiff = 1.000000e003 targ= 1.083343e003 trig= 8.334295e005
Measure statement example:
.measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=3
measures the time difference between v(1) reaching 0.5 V for the first time on its rising slope versus reaching 0.5 V on its rising slope for the third time (i.e. two periods).
Measure statement:
.measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 FALL=1
measures the time difference between v(1) reaching 0.5V for the first time on its rising slope versus reaching 0.5 V on its first falling slope.
Measure statement:
.measure tran tdiff TRIG v(1) VAL=0 FALL=3 TARG v(2) VAL=0 FALL=3
measures the time difference between v(1) reaching 0V its third falling slope versus v(2) reaching 0 V on its third falling slope.
Measure statement:
.measure tran tdiff TRIG v(1) VAL=0.6 CROSS=1 TARG v(2) VAL=0.8 CROSS=1
measures the time difference between v(1) crossing 0.6 V for the first time (any slope) versus v(2) crossing 0.8 V for the first time (any slope).
Measure statement:
.measure tran tdiff TRIG AT=1m TARG v(2) VAL=0.8 CROSS=3
measures the time difference between the time point 1ms versus the time when v(2) crosses 0.8 V for the third time (any slope).
Find ... When
The FIND and WHEN functions allow to measure any dependent or independent time, frequency, or dc parameter, when two signals cross each other or a signal crosses a given value. Measurements start after a delay TD and may be restricted to a range between FROM and TO.
General form 2:
.MEASURE {DCACTRANSP} result WHEN out_variable=val
+ <TD=td> <FROM=val> <TO=val> <CROSS=#  CROSS=LAST>
+ <RISE=#  RISE=LAST> <FALL=#  FALL=LAST>
Measure statement:
.measure tran teval WHEN v(2)=0.7 CROSS=LAST
measures the time point when v(2) crosses 0.7 V for the last time (any slope).
General form 3:
.MEASURE {DCACTRANSP} result
+ WHEN out_variable=out_variable2
+ <TD=td> <FROM=val> <TO=val> <CROSS=#  CROSS=LAST>
+ <RISE=#  RISE=LAST> <FALL=#  FALL=LAST>
Measure statement:
.measure tran teval WHEN v(2)=v(1) RISE=LAST
measures the time point when v(2) and v(1) are equal, v(2) rising for the last time.
General form 4:
.MEASURE {DCACTRANSP} result FIND out_variable
+ WHEN out_variable2=val <TD=td> <FROM=val> <TO=val>
+ <CROSS=#  CROSS=LAST> <RISE=#  RISE=LAST>
+ <FALL=#  FALL=LAST>
Measure statement:
.measure tran yeval FIND v(2) WHEN v(1)=0.4 FALL=LAST
returns the dependent (y) variable drawn from v(2) at the time point when v(1) equals a value of 0.4, v(1) falling for the last time.
General form 5:
.MEASURE {DCACTRANSP} result FIND out_variable
+ WHEN out_variable2=out_variable3 <TD=td>
+ <CROSS=#  CROSS=LAST>
+ <RISE=#RISE=LAST> <FALL=#FALL=LAST>
Measure statement:
.measure tran yeval FIND v(2) WHEN v(1)=v(3) FALL=2
returns the dependent (y) variable drawn from v(2) at the time point when v(1) crosses v(3), v(1) falling for the second time.
General form 6:
.MEASURE {DCACTRANSP} result FIND out_variable AT=val
Measure statement:
.measure tran yeval FIND v(2) AT=2m
returns the dependent (y) variable drawn from v(2) at the time point 2 ms (given by AT=time).
AVGMINMAXPPRMSMIN_ATMAX_AT
General form 7:
.MEASURE {DCACTRANSP} result
+ {AVGMINMAXPPRMSMIN_ATMAX_AT}
+ out_variable <TD=td> <FROM=val> <TO=val>
Measure statements:
.measure tran ymax MAX v(2) from=2m to=3m
returns the maximum value of v(2) inside the time interval between 2 ms and 3 ms.
.measure tran tymax MAX_AT v(2) from=2m to=3m
returns the time point of the maximum value of v(2) inside the time interval between 2 ms and 3 ms.
.measure tran ypp PP v(1) from=2m to=4m
returns the peak to peak value of v(1) inside the time interval between 2 ms and 4 ms.
.measure tran yrms RMS v(1) from=2m to=4m
returns the root mean square value of v(1) inside the time interval between 2 ms and 4 ms.
.measure tran yavg AVG v(1) from=2m to=4m
returns the average value of v(1) inside the time interval between 2 ms and 4 ms.
Integ
General form 8:
.MEASURE {DCACTRANSP} result INTEG<RAL> out_variable
+ <TD=td> <FROM=val> <TO=val>
Measure statement:
.measure tran yint INTEG v(2) from=2m to=3m
returns the area under v(2) inside the time interval between 2 ms and 3 ms.
param
General form 9:
.MEASURE {DCACTRANSP} result param='expression'
Measure statement:
.param fval=5
.measure tran yadd param='fval + 7'
will evaluate the given expression fval + 7 and return the value 12.
'Expression' is evaluated according to the rules given in Chapt. 2.8.5 during start up of ngspice. It may contain parameters defined with the .param statement. It may also contain parameters resulting from preceding .meas statements.
.param vout_diff=50u
...
.measure tran tdiff TRIG AT=1m TARG v(2) VAL=0.8 CROSS=3
.meas tran bw_chk param='(tdiff < vout_diff) ? 1 : 0'
will evaluate the given ternary function and return the value 1 in bw_chk, if tdiff measured is smaller than parameter vout_diff.
The expression may not contain vectors like v(10), e.g. anything resulting directly from a simulation. This may be handled with the following .meas command option.
par('expression')
The par('expression') option (15.6.6) allows to use algebraic expressions on the .measure lines. Every out_variable may be replaced by par('expression') using the general forms 1…9 described above. Internally par('expression') is substituted by a vector according to the rules of the B source (Chapt. 5.1). A typical example of the general form is shown below:
General form 10:
.MEASURE {DCTRANACSP} result
+ FIND par('expression') AT=val
The measure statement
.measure tran vtest find par('(v(2)*v(1))') AT=2.3m
returns the product of the two voltages at time point 2.3 ms.
Note that a Bsource, and therefore the par('...') feature, operates on values of type complex in AC analysis mode.
Deriv
General form:
.MEASURE {DCACTRANSP} result DERIV<ATIVE> out_variable
+ AT=val
.MEASURE {DCACTRANSP} result DERIV<ATIVE> out_variable
+ WHEN out_variable2=val <TD=td>
+ <CROSS=#  CROSS=LAST> <RISE=#RISE=LAST>
+ <FALL=#FALL=LAST>
.MEASURE {DCACTRANSP} result DERIV<ATIVE> out_variable
+ WHEN out_variable2=out_variable3
+ <TD=td> <CROSS=#  CROSS=LAST>
+ <RISE=#RISE=LAST> <FALL=#FALL=LAST>
More examples
Some other examples, also showing the use of parameters, are given below. Corresponding demonstration input files are distributed with ngspice in folder /examples/measure.
Other examples:
.meas tran inv_delay2 trig v(in) val='vp/2' td=1n fall=1
+ targ v(out) val='vp/2' rise=1
.meas tran test_data1 trig AT = 1n targ v(out)
+ val='vp/2' rise=3
.meas tran out_slew trig v(out) val='0.2*vp' rise=2
+ targ v(out) val='0.8*vp' rise=2
.meas tran delay_chk param='(inv_delay < 100ps) ? 1 : 0'
.meas tran skew when v(out)=0.6
.meas tran skew2 when v(out)=skew_meas
.meas tran skew3 when v(out)=skew_meas fall=2
.meas tran skew4 when v(out)=skew_meas fall=LAST
.meas tran skew5 FIND v(out) AT=2n
.meas tran v0_min min i(v0)
+ from='dfall' to='dfall+period'
.meas tran v0_avg avg i(v0)
+ from='dfall' to='dfall+period'
.meas tran v0_integ integ i(v0)
+ from='dfall' to='dfall+period'
.meas tran v0_rms rms i(v0)
+ from='dfall' to='dfall+period'
.meas dc is_at FIND i(vs) AT=1
.meas dc is_max max i(vs) from=0 to=3.5
.meas dc vds_at when i(vs)=0.01
.meas ac vout_at FIND v(out) AT=1MEG
.meas ac vout_atd FIND vdb(out) AT=1MEG
.meas ac vout_max max v(out) from=1k to=10MEG
.meas ac freq_at when v(out)=0.1
.meas ac vout_diff trig v(out) val=0.1 rise=1 targ v(out)
+ val=0.1 fall=1
.meas ac fixed_diff trig AT = 10k targ v(out)
+ val=0.1 rise=1
.meas ac vout_avg avg v(out) from=10k to=1MEG
.meas ac vout_integ integ v(out) from=20k to=500k
.meas ac freq_at2 when v(out)=0.1 fall=LAST
.meas ac bw_chk param='(vout_diff < 100k) ? 1 : 0'
.meas ac vout_rms rms v(out) from=10 to=1G
Safe Operating Area (SOA) warning messages
By setting .option warn=1 the Safe Operation Area check algorithm is enabled. In this case for .op, .dc and .tran analysis warning messages are issued if the branch voltages of devices (Resistors, Capacitors, Diodes, BJTs and MOSFETs) exceed limits that are specified by model parameters. All these parameters are positive with default value of infinity.
The check is executed after NewtonRaphson iteration is finished i.e. in transient analysis in each time step. The user can specify an additional .option maxwarns (default: 5) to limit the count of messages.
The output goes on default to stdout or alternatively to a file specified by command line option soalog=filename.
Resistor and Capacitor SOA model parameters
 Bv_max:if Vr or Vc exceed Bv_max, SOA warning is issued.
Diode SOA model parameter
 Bv_max:if Vj exceeds Bv_max, SOA warning is issued.
 Fv_max:if Vf exceeds Fv_max, SOA warning is issued.
BJT SOA model parameter
 Vbe_max:if Vbe exceeds Vbe_max, SOA warning is issued.
 Vbc_max:if Vbc exceeds Vbc_max, SOA warning is issued.
 Vce_max:if Vce exceeds Vce_max, SOA warning is issued.
 Vcs_max:if Vcs exceeds Vcs_max, SOA warning is issued.
MOS SOA model parameter
 Vgs_max:if Vgs exceeds Vgs_max, SOA warning is issued.
 Vgd_max:if Vgd exceeds Vgd_max, SOA warning is issued.
 Vgb_max:if Vgb exceeds Vgb_max, SOA warning is issued.
 Vds_max:if Vds exceeds Vds_max, SOA warning is issued.
 Vbs_max:if Vbs exceeds Vbs_max, SOA warning is issued.
 Vbd_max:if Vbd exceeds Vbd_max, SOA warning is issued.
Batch Output
The following commands .print (15.6.2), .plot (15.6.3) and .four (15.6.4) are valid only if ngspice is started in batch mode (see 16.4.1), whereas .save and the equivalent .probe are aknowledged in all operating modes.
If you start ngspice in batch mode using the b command line option, the outputs of .print, .plot, and .four are printed to the console output. You may use the output redirection of your shell to direct this printout into a file (not available with MS Windows GUI). As an alternative you may extend the ngspice command by specifying an output file:
ngspice b o output.log input.cir
If you however add the command line option r to create a rawfile, .print and .plot are ignored. If you want to involve the graphics plot output of ngspice, use the control mode (16.4.3) instead of the b batch mode option.
.SAVE: Name vector(s) to be saved in raw file
General form:
.save vector vector vector ...
Examples:
.save i(vin) node1 v(node2)
.save @m1[id] vsource#branch
.save all @m2[vdsat]
The vectors listed on the .SAVE line are recorded in the rawfile for use later with ngspice or ngnutmeg (ngnutmeg is just the dataanalysis half of ngspice, without the ability to simulate). The standard vector names are accepted. Node voltages may be saved by giving the nodename or v(nodename). Currents through an independent voltage source are given by i(sourcename) or sourcename#branch. Internal device data are accepted as @dev[param].
If no .SAVE line is given, then the default set of vectors is saved (node voltages and voltage source branch currents). If .SAVE lines are given, only those vectors specified are saved. For more discussion on internal device data, e.g. @m1[id], see Appendix, Chapt. 31.1. If you want to save internal data in addition to the default vector set, add the parameter all to the additional vectors to be saved. If the command .save vm(out) is given, and you store the data in a rawfile, only the original data v(out) are stored. The request for storing the magnitude is ignored, because this may be added later during rawfile data evaluation with ngnutmeg or ngspice. See also the section on the interactive command interpreter (Chapt. 17.5) for information on how to use the rawfile.
.PRINT Lines
General form:
.print prtype ov1 <ov2 ... ov8>
Examples:
.print tran v(4) i(vin)
.print dc v(2) i(vsrc) v(23, 17)
.print ac vm(4, 2) vr(7) vp(8, 3)
The .print line defines the contents of a tabular listing of one to eight output variables. prtype is the type of the analysis (DC, AC, TRAN, NOISE, or DISTO) for which the specified outputs are desired. The form for voltage or current output variables is the same as given in the previous section for the print command; Spice2 restricts the output variable to the following forms (though this restriction is not enforced by ngspice):
V(N1<,N2>)

specifies the voltage difference between nodes N1 and N2. If N2 (and the preceding comma) is omitted, ground (0) is assumed. See the print command in the previous section for more details. For compatibility with SPICE2, the following five additional values can be accessed for the ac analysis by replacing the `V' in V(N1,N2) with:




I(VXXXXXXX)

specifies the current flowing in the independent voltage source named VXXXXXXX. Positive current flows from the positive node, through the source, to the negative node. (Not yet implemented: For the ac analysis, the corresponding replacements for the letter I may be made in the same way as described for voltage outputs.)

Output variables for the noise and distortion analyses have a different general form from that of the other analyses. There is no limit on the number of .print lines for each type of analysis. The par**('expression')** option (15.6.6) allows to use algebraic expressions in the .print lines. .width (15.6.7) selects the maximum number of characters per line.
.PLOT Lines
.plot creates a printer plot output.
General form:
.plot pltype ov1 <(plo1, phi1)> <ov2 <(plo2, phi2)> ... ov8>
Examples:
.plot dc v(4) v(5) v(1)
.plot tran v(17, 5) (2, 5) i(vin) v(17) (1, 9)
.plot ac vm(5) vm(31, 24) vdb(5) vp(5)
.plot disto hd2 hd3(R) sim2
.plot tran v(5, 3) v(4) (0, 5) v(7) (0, 10)
The .plot line defines the contents of one plot of from one to eight output variables. pltype is the type of analysis (DC, AC, TRAN, NOISE, or DISTO) for which the specified outputs are desired. The syntax for the ovi is identical to that for the .print line and for the plot command in the interactive mode.
The overlap of two or more traces on any plot is indicated by the letter `X'. When more than one output variable appears on the same plot, the first variable specified is printed as well as plotted. If a printout of all variables is desired, then a companion .print line should be included. There is no limit on the number of .plot lines specified for each type of analysis. The par('expression') option (15.6.6) allows to use algebraic expressions in the .plot lines.
.FOUR: Fourier Analysis of Transient Analysis Output
General form:
.four freq ov1 <ov2 ov3 ...>
Examples:
.four 100K v(5)
The .four (or Fourier) line controls whether ngspice performs a Fourier analysis as a part of the transient analysis. freq is the fundamental frequency, and ov1 is the desired vector to be analyzed. The Fourier analysis is performed over the interval <TSTOPperiod, TSTOP>, where TSTOP is the final time specified for the transient analysis, and period is one period of the fundamental frequency. The dc component and the first nine harmonics are determined. For maximum accuracy, TMAX (see the .tran line) should be set to period/100.0 (or less for very highQ circuits). The par('expression') option (15.6.6) allows to use algebraic expressions in the .four lines.
.PROBE: Name vector(s) to be saved in raw file
General form:
.probe vector <vector vector ...>
Examples:
.probe i(vin) input output
.probe @m1[id]
Same as .SAVE (see Chapt. 15.6.1).
par('expression'): Algebraic expressions for output
General form:
par('expression')
output=par('expression') $ not in .measure ac
Examples:
.four 1001 sq1=par('v(1)*v(1)')
.measure tran vtest find par('(v(2)*v(1))') AT=2.3m
.print tran output=par('v(1)/v(2)') v(1) v(2)
.plot dc v(1) diff=par('(v(4)v(2))/0.01') out222
With the output lines .four, .plot, .print, .save and in .measure evaluation it is possible to add algebraic expressions for output, in addition to vectors. All of these output lines accept par**('expression')**, where expression is any expression valid for a B source (see Chapt. 5.1). Thus expression may contain predefined functions, numerical values, constants, simulator output like v(n1) or i(vdb), parameters predefined by a .param statement, and the variables hertz, temper, and time. Note that a Bsource, and therefore the par('...') feature, operates on values of type complex in AC analysis mode.
Internally the expression is replaced by a generated voltage node that is the output of a B source, one node, and the B source implementing par**('...')**. Several par('...') are allowed in each line, up to 99 per input file. The internal nodes are named pa_00 to pa_99. An error will occur if the input file contains any of these reserved node names.
In .four, .plot, .print, .save, but not in .measure, an alternative
syntax
output**=par('expression') is possible. par('expression')
may be used as described above. output is the name of the new node to
replace the expression. So output has to be unique and a valid node
name.
The syntax of output**=par(expression)** is strict, no spaces between par and (', or between ( and ' are allowed, (' and ') both are required. Also there is not much error checking on your input, if there is a typo, for example, an error may pop up at an unexpected place.
.width
Set the width of a printout or plot with the following card:
.with out = 256
Parameter out yields the maximum number of characters plotted in a row, if printing in columns or an ASCIIplot is selected.
Measuring current through device terminals
Adding a voltage source in series
Originally the ngspice matrix solver delivers node voltages and currents through independent voltage sources. So to measure the currents through a resistor you may add a voltage source in series with dc voltage 0.
Current measurement with series voltage source
*measure current through R1
V1 1 0 1
R1 1 0 5
R2 1 0 10
* will become
V1 1 0 1
R1 1 11 5
Vmess 11 0 dc 0
R2 1 0 10
Using option 'savecurrents'
Current measurement with series voltage source
*measure current through R1 and R2
V1 1 0 1
R1 1 0 5
R2 1 0 10
.options savecurrents
The option savecurrents will add .save lines (15.6.1) like
.save @r1[i]
.save @r2[i]
to your input file information read during circuit parsing. These newly created vectors contain the terminal currents of the devices R1 and R2.
You will find information of the nomenclature in Chapt. 31, also how to plot these vectors. The following devices are supported: M, J, Q, D, R, C, L, B, F, G, W, S, I (see 2.1.2). For M only MOSFET models MOS1 to MOS9 are included so far. Devices in subcircuits are supported as well. Be careful when choosing this option in larger circuits, because 1 to 4 additional output vectors are created per device and this may consume lots of memory.
Starting ngspice
Introduction
Ngspice consists of the simulator and a frontend for data analysis and plotting. Input to the simulator is a netlist file, including commands for circuit analysis and output control. Interactive ngspice can plot data from a simulation on a PC or a workstation display.
Ngspice on Linux (and OSs like Cygwin, BCD, Solaris ...) uses the X Window System for plotting (see Chapt. 18.3) if the environment variable DISPLAY is available. Otherwise, a console mode (nongraphical) interface is used. If you are using X on a workstation, the DISPLAY variable should already be set; if you want to display graphics on a system different from the one you are running ngspice or ngutmeg on, DISPLAY should be of the form machine:0.0. See the appropriate documentation on the X Window System for more details.
The MS Windows versions of ngspice and ngnutmeg will have a native graphics interface (see Chapt. 18.1).
The frontend may be run as a separate `standalone' program under the name ngnutmeg. ngnutmeg is a subset of ngspice dedicated to data evaluation, still made available for historical reasons. Ngnutmeg will read in the `raw' data output file created by ngspice r or by the write command during an interactive ngspice session.
Where to obtain ngspice
The actual distribution of ngspice may be downloaded from the ngspice download web page. The installation for Linux or MS Windows is described in the file INSTALL to be found in the top level directory. You may also have a look at Chapt. 32 of this manual for compiling instructions.
If you want to check out the source code that is actually under development, you may have a look at the ngspice source code repository, which is stored using the Git Source Code Management (SCM) tool. The Git repository may be browsed on the Git web page, also useful for downloading individual files. You may however download (or clone) the complete repository including all source code trees from the console window (Linux, CYGWIN or MSYS/MINGW) by issuing the command (in a single line)
git clone git://git.code.sf.net/p/ngspice/ngspice
You need to have Git installed, which is available for all three OSs. The whole source tree is then available in <current directory>/ngspice. Compilation and local installation is again described in INSTALL (or Chapt. 32). If you later want to update your files and download the recent changes from sourceforge into your local repository, cd into the ngspice directory and just type
git pull
git pull will deny to overwrite modified files in your working directory. To drop your local changes first, you can run
git reset hard
To learn more about git, which can be both powerful and difficult to master, please consult http://gitscm.com/, especially: http://gitscm.com/documentation, which has pointers to documentation and tutorials.
Command line options for starting ngspice and ngnutmeg
Command Synopsis:
ngspice [ o logfile] [ r rawfile] [ b ] [ i ] [ input files ]
ngnutmeg [  ] [ datafile ... ]
Options are:
Option

Long option

Meaning



Don't try to load the default data file ("rawspice.raw") if no other files are given (ngnutmeg only).


n

nospiceinit

Don't try to source the file .spiceinit upon startup. Normally ngspice and ngnutmeg try to find the file in the current directory, and if it is not found then in the user's home directory (obsolete).

t TERM

terminal=TERM

The program is being run on a terminal with mfb name term (obsolete).

b

batch

Run in batch mode. Ngspice reads the default input source (e.g. keyboard) or reads the given input file and performs the analyses specified; output is either Spice2like lineprinter plots ("ascii plots") or a ngspice rawfile. See the following section for details. Note that if the input source is not a terminal (e.g. using the IO redirection notation of "<") ngspice defaults to batch mode (i overrides). This option is valid for ngspice only.

s

server

Run in server mode. This is like batch mode, except that a temporary rawfile is used and then written to the standard output, preceded by a line with a single "@", after the simulation is done. This mode is used by the ngspice daemon. This option is valid for ngspice only.
Example for using pipes from the console window:
cat adder.cirngspice smore

i

interactive

Run in interactive mode. This is useful if the standard input is not a terminal but interactive mode is desired. Command completion is not available unless the standard input is a terminal, however. This option is valid for ngspice only.

r FILE

rawfile=FILE

Use rawfile as the default file into which the results of the simulation are saved. This option is valid for ngspice only.

p

pipe

Allow a program (e.g., xcircuit) to act as a GUI frontend for ngspice through a pipe. Thus ngspice will assume that the input pipe is a tty and allows to run in interactive mode.

o FILE

output=FILE

All logs generated during a batch run (b) will be saved in outfile.

h

help

A short help statement of the command line syntax.

v

version

Prints a version information.

a

autorun

Start simulation immediately, as if a control section
.control
run
.endc
had been added to the input file.

soalog=FILE

output from Safe Operating Area (SOA) check

Further arguments to ngspice are taken to be ngspice input files, which are read and saved (if running in batch mode then they are run immediately). Ngspice accepts Spice3 (and also most Spice2) input files, and outputs ASCII plots, Fourier analyses, and node printouts as specified in .plot, .four, and .print cards. If an out parameter is given on a .width card (15.6.7), the effect is the same as set width = .... Since ngspice ASCII plots do not use multiple ranges, however, if vectors together on a .plot card have different ranges they do not provide as much information as they do in a scalable graphics plot.
For ngnutmeg, further arguments are taken to be data files in binary or ASCII raw file format (generated with r in batch mode or the write (see 17.5.93) command) that are loaded into ngnutmeg. If the file is in binary format, it may be only partially completed (useful for examining output before the simulation is finished). One file may contain any number of data sets from different analyses.
Starting options
Batch mode
Let's take as an example the FourBit binary adder MOS circuit shown in Chapt. 21.6, stored in a file addermos.cir. You may start the simulation immediately by calling
ngspice b r adder.raw o adder.log addermos.cir
ngspice will start, simulate according to the .tran command and store the output data in a rawfile adder.raw. Comments, warnings and infos go to log file adder.log. Commands for batch mode operation are described in Chapt. 15.
Interactive mode
If you call
ngspice
ngspice will start, load spinit (16.5) and .spiceinit (16.6, if available), and then waits for your manual input. Any of the commands described in 17.5 may be chosen, but many of them are useful only after a circuit has been loaded by
ngspice 1 > source addermos.cir
others require the simulation being done already (e.g. plot):
ngspice 2 >run
ngspice 3 >plot allv
If you call ngspice from the command line with a circuit file as parameter:
ngspice addermos.cir
ngspice will start, load the circuit file, parse the circuit (same circuit file as above, containing only dot commands (see Chapt. 15) for analysis and output control). ngspice then just waits for your input. You may start the simulation by issuing the run command. Following completion of the simulation you may analyze the data by any of the commands given in Chapt. 17.5.
Control mode (Interactive mode with control file or control section)
If you add the following control section to your input file addermos.cir, you may call
ngspice addermos.cir
from the command line and see ngspice starting, simulating and then plotting immediately.
Control section:
* ADDER  4 BIT ALLNANDGATE BINARY ADDER
.control
unset askquit
save vcc#branch
run
plot vcc#branch
rusage all
.endc
Any suitable command listed in Chapt. 17.5 may be added to the control section, as well as control structures described in Chapt. 17.6. Batchlike behavior may be obtained by changing the control section to
Control section with batchlike behavior:
* ADDER  4 BIT ALLNANDGATE BINARY ADDER
.control
unset askquit
save vcc#branch
run
write adder.raw vcc#branch
quit
.endc
If you put this control section into a file, say adderstart.sp, you may just add the line
.include adderstart.sp
to your input file addermos.cir to obtain the batchlike behavior. In the following example the line .tran ... from the input file is overridden by the tran command given in the control section.
Control section overriding the .tran command:
* ADDER  4 BIT ALLNANDGATE BINARY ADDER
.control
unset askquit
save vcc#branch
tran 1n 500n
plot vcc#branch
rusage all
.endc
The commands within the .control section are executed in the order they are listed and only after the circuit has been read in and parsed. If you want to have a command being executed before circuit parsing, you may use the prefix pre_ (17.5.49) to the command.
A warning is due however: If your circuit file contains such a control section (.control ... .endc), you should not start ngspice in batch mode (with b as parameter). The outcome may be unpredictable!
Standard configuration file spinit
At startup ngspice reads its configuration file spinit. spinit may be
found in a path relative to the location of the ngspice executable
..\share\ngspice\scripts. The path may be overridden by setting the
environmental variable SPICE_SCRIPTS to a path where spinit is located.
Ngspice for Windows will additionally search for spinit in the directory
where ngspice.exe resides. If spinit is not found a warning message is
issued, but ngspice continues.
Standard spinit contents:
* Standard ngspice init file
alias exit quit
alias acct rusage all
** set the number of threads in openmp
** default (if compiled with enableopenmp) is: 2
set num_threads=4
if $?sharedmode
unset interactive
unset moremode
else
set interactive
set x11lineararcs
end
strcmp __flag $program "ngspice"
if $__flag = 0
codemodel ../lib/spice/spice2poly.cm
codemodel ../lib/spice/analog.cm
codemodel ../lib/spice/digital.cm
codemodel ../lib/spice/xtradev.cm
codemodel ../lib/spice/xtraevt.cm
codemodel ../lib/spice/table.cm
end
unset __flag
spinit contains a script, made of commands from Chapt. 17.5, that is run upon start up of ngspice. Aliases (name equivalences) can be set. The asterisk `*' comments out a line. If used by ngspice, spinit will then load the XSPICE code models from a path relative to the current directory where the ngspice executable resides. You may also define absolute paths.
If the standard path for the libraries (see standard spinit above or /usr/local/lib/spice under CYGWIN and Linux) is not adequate, you can add the ./configure options prefix=/usr libdir=/usr/lib64 to set the codemodel search path to /usr/lib64/spice. Besides the standard lib only lib64 is acknowledged.
Special care has to be taken when using the ngspice shared library. If you apply ngspice.dll under Windows OS, the standard is to use relative paths for the code models as shown above. However, the path is relative to the calling program, not to the dll. This is fine when ngspice.dll and the calling program reside in the same directory. If ngspice.dll is placed in a different directory, please check Chapt. 32.2.
The Linux shared library ... t.b.d.
User defined configuration file .spiceinit
In addition to spinit you may define a (personal) file .spiceinit and put it into the current directory or in your home directory. The typical search sequence for .spiceinit is: current directory, HOME (Linux) and then USERPROFILE (Windows). USERPROFILE is typically C:\Users\<User name>. This file will be read in and executed after spinit, but before any other input file is read. It may contain further scripts, set variables, or issue commands from Chapt.17.5 to override commands given in spinit. For example set filetype=ascii will yield ASCII output in the output data file (rawfile), instead of the compact binary format that is used by default. set ngdebug will yield a lot of additional debug output. Any other contents of the script, e.g. plotting preferences, may be included here also. If the command line option n is used upon ngspice start up, this file will be ignored.
.spiceinit may contain:
* User defined ngspice init file
set filetype=ascii
*set ngdebug
set numthreads = 8
*set outputpath=C:\Spice64\out
Environmental variables
Ngspice specific variables
 SPICE_LIB_DIR
default: /usr/local/share/ngspice (Linux, CYGWIN), C:\Spice\share\ngspice (Windows)  SPICE_EXEC_DIR
default: /usr/local/bin (Linux, CYGWIN), C:\Spice\bin (Windows)  SPICE_BUGADDR
default: http://ngspice.sourceforge.net/bugrep.html
Where to send bug reports on ngspice.  SPICE_EDITOR
default: vi (Linux, CYGWIN), notepad.exe (MINGW, Visual Studio)
Set the editor called in the edit command. Always overrides the EDITOR env. variable.  SPICE_ASCIIRAWFILE
default: 0
Format of the rawfile. 0 for binary, and 1 for ascii.  SPICE_NEWS
default: $SPICE_LIB_DIR/news
A file that is copied verbatim to stdout when ngspice starts in interactive mode.  SPICE_HELP_DIR
default: $SPICE_LIB_DIR/helpdir
Help directory, not used in Windows mode  SPICE_HOST
default: empty string
Used in the rspice command (probably obsolete, to be documented)  SPICE_SCRIPTS
default: $SPICE_LIB_DIR/scripts
In this directory the spinit file will be searched.  SPICE_PATH
default: $SPICE_EXEC_DIR/ngspice
Used in the aspice command (probably obsolete, to be documented)  NGSPICE_MEAS_PRECISION
default: 5
Sets the number of digits if output values are printed by the meas(ure) command.  SPICE_NO_DATASEG_CHECK
default: undefined
If defined, will suppress memory resource info (probably obsolete, not used on Windows or where the /proc information system is available.)  NGSPICE_INPUT_DIR
default: undefined
If defined, using a valid directory name, will add the given directory to the search path when looking for input files (*.cir, *.inc, *.lib).
Common environment variables
TERM LINES COLS DISPLAY HOME PATH EDITOR SHELL POSIXLY_CORRECT
Memory usage
Ngspice started with batch option (b) and rawfile output (r rawfile) will store all simulation data immediately into the rawfile without keeping them in memory. Thus very large circuits may be simulated, the memory requested upon ngspice start up will depend on the circuit size, but will not increase during simulation.
If you start ngspice in interactive mode or interactively with control section, all data will be kept in memory, to be available for later evaluation. A large circuit may outgrow even Gigabytes of memory. The same may happen after a very long simulation run with many vectors and many time steps to be stored. Issuing the save <nodes> command will help to reduce memory requirements by saving only the data defined by the command. You may alos choose option INTERP (15.1.4) to reduce memory usage.
Simulation time
Simulating large circuits may take an considerable amount of CPU time. If this is of importance, you should compile ngspice with the flags for optimum speed, set during configuring ngspice compilation. Under Linux, MINGW, and CYGWIN you should select the following option to disable the debug mode, which slows down ngspice:
./configure disabledebug
Adding disabledebug will set the O2 optimization flag for compiling and linking.
Under MS Visual Studio, you will have to select the release version, which includes optimization for speed.
If you have selected XSPICE (see Chapt. 12 and II) as part of your compilation configuration (by adding the option enablexspice to your ./configure command), the value of trtol (see 15.1.4) is set internally to 1 (instead of default 7) for higher precision if XSPICE code model 'A' devices included in the circuit. This may double or even triple the CPU time needed for any transient simulation, because the amount of time steps and thus iteration steps is more than doubled. For MS Visual Studio compilation there is currently no simple way to exclude XSPICE during compilation.
You may enforce higher speed during XSPICE usage by setting the variable xtrtol in your .spiceinit initialization file or in the .control section in front of the tran command (via set xtrtol=2 using the set command 17.5.63) and override the above trtol reduction. Beware however of precision or convergence issues if you use XSPICE 'A' devices, especially if xtrtol is set to values larger than 2.
If your circuit comprises mostly of MOS transistors, and you have a multicore processor at hand, you may benefit from OpenMP parallel processing, as described next (16.10).
Ngspice on multicore processors using OpenMP
Introduction
Today's computers typically come with CPUs having more than one core. It will thus be useful to enhance ngspice to make use of such multicore processors.
Using circuits comprising mostly of transistors and e.g. the BSIM3 model, around 2/3 of the CPU time is spent in evaluating the model equations (e.g. in the BSIM3Load() function). The same happens with other advanced transistor models. Thus this function should be paralleled, if possible. Resulting from that the parallel processing has to be within a dedicated device model. Solving the matrix takes about 10% to 50% of the CPU time, so paralleling the matrix solver is sometimes of secondary interest only! And it is difficult to achive with our Sparse Matrix und KLU solvers.
Another alternative is using CUSPICE, that is ngspice (current version
 designed for running massively parallel on NVIDIA GPUs. CUDA enhancements to C code are applied. For LINUX, please see the user guide. For MS Windows, an executable is available at the ngspice download pages.
Internals
A recent publication [1] has described a way to exactly do that using OpenMP, which is available on many platforms and is easy to use, especially if you want to parallel processing of a forloop.
To explain the implemented approach BSIM3 version 3.3.0 model was chosen, located in the BSIM3 directory, as the first example. The BSIM3load() function in b3ld.c contains two nested forloops using linked lists (models and instances, e.g. individual transistors). Unfortunately OpenMP requires a loop with an integer index. So in file B3set.c an array is defined, filled with pointers to all instances of BSIM3 and stored in model>BSIM3InstanceArray.
BSIM3load() is now a wrapper function, calling the forloop, which runs through functions BSIM3LoadOMP(), once per instance. Inside BSIM3LoadOMP() the model equations are calculated.
Typically need it is needed to synchronize the activities, in that storing the results into the matrix has to be guarded. The trick offered by the authors now is that the storage is moved out of the BSIM3LoadOMP() function. Inside BSIM3LoadOMP() the updated data are stored in extra locations locally per instance, defined in bsim3def.h. Only after the complete forloop is exercised, the update to the matrix is done in an extra function BSIM3LoadRhsMat() in the main thread after the paralleled loop. No extra synchronization is required.
Then the thread programming needed is only a single line!!
#pragma omp parallel for
introducing the forloop over the device instances.
This of course is made possible only thanks to the OpenMP guys and the clever trick on no synchronization introduced by the above cited authors.
The timemeasuring function getrusage() used with Linux or Cygwin to determine the CPU time usage (with the rusage option enabled) counts tics from every core, adds them up, and thus reports a CPU time value enlarged by a factor of 8 if 8 threads have been chosen. So now ngspice is forced to use ftime for time measuring if OpenMP is selected.
Some results
Some results on an inverter chain with 627 CMOS inverters, running for 200ns, compiled with Visual Studio professional 2008 on Windows 7 (full optimization) or gcc 4.4, SUSE Linux 11.2, O2, on a i7 860 machine with four real cores (and 4 virtuals using hyperthreading) are shown in table 16.1.
Table 16.1: OpenMP performance
Threads

CPU time [s]

CPU time [s]

Windows

Linux


1 (standard)

167

165

1 (OpenMP)

174

167

2

110

110

3

95

94120

4

83

107

6

94

90

8

93

91

So we see a ngspice speed up of nearly a factor of two! Even on an older notebook with a dual core processor, more than 1.5x improvement using two threads was attained. Similar results are to be expected from BSIM4.
Usage
To state it clearly: OpenMP is installed inside the model equations of a particular model. It is available in BSIM3 versions 3.3.0 and 3.2.4, but not in any other BSIM3 model, in BSIM4 versions 4.5, 4.6.5, 4.7 or 4.8, but not in any other BSIM4 model, and in B4SOI, version 4.4, not in any other SOI model. Older parameter files of version 4.6.x (x any number up to 5) are accepted, you have to check for compatibility.
Under Linux you may run
./autogen.sh
./configure ... enableopenmp
make install
The same has been tested under MS Windows with CYGWIN and MINGW as well and delivers similar results.
Under MS Windows with Visual Studio Professional the preprocessor flag USE_OMP, and the /openmp flag in Visual Studio are enabled by default. Visual Studio 2015 or 2017 offer OpenMP support inherently.
The number of threads has to be set manually by placing
set num_threads=4
into spinit or .spiceinit or in the control section of the SPICE input file. If OpenMP is enabled, but num_threads not set, a default value num_threads=2 is set internally.
If you simulate a circuit, please keep in mind to select BSIM3 (levels 8, 49) version 3.2.4 or 3.3.0 (11.2.10), by placing this version number into your parameter files, BSIM4 (levels 14,
 version 4.5, 4.6.5, 4.7 or 4.8 (11.2.11), or B4SOI (levels 10, 58) version 4.4 (11.2.13). All other transistor models run as usual (without multithreading support).
If you run ./configure without enableopenmp (or without USE_OMP preprocessor flag under MS Windows), you will get only the standard, not paralleled BSIM3 and BSIM4 models, as has been available from Berkeley. If OpenMP is selected and the number of threads set to 1, there will be only a very slight CPU time disadvantage (typ. 3%) compared to the old, non OpenMP build.
Literature
[1] R.K. Perng, T.H. Weng, and K.C. Li: "On Performance Enhancement of Circuit Simulation Using Multithreaded Techniques", IEEE International Conference on Computational Science and Engineering, 2009, pp. 158165
Server mode option s
A program may write the SPICE input to the console. This output is redirected to ngspice via `'. ngspice called with the s option writes its output to the console, which again is redirected to a receiving program by `'. In the following simple example cat reads the input file and prints it content to the console, which is redirected to ngspice by a first pipe, ngspice transfers its output (similar to a raw file, see below) to less via another pipe.
Example command line:
cat input.cirngspice sless
Under MS Windows you will need to compile ngspice as a console application (see Chapt. 32.2.5) for this server mode usage.
Example input file:
test s
v1 1 0 1
r1 1 0 2k
.options filetype=ascii
.save i(v1)
.dc v1 1 1 0.5
.end
If you start ngspice console with
ngspice s
you may type in the above circuit line by line (not to forget the first line, which is a title and will be ignored). If you close your input with ctrl Z, and return, you will get the following output (this is valid for MINGW only) on the console, like a raw file:
Circuit: test s
Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
Title: test s
Date: Sun Jan 15 18:57:13 2012
Plotname: DC transfer characteristic
Flags: real
No. Variables: 2
No. Points: 0
Variables:
No. of Data Columns : 2
0 v(vsweep) voltage
1 i(v1) current
Values:
0 1.000000000000000e+000
5.000000000000000e004
1 5.000000000000000e001
2.500000000000000e004
2 0.000000000000000e+000
0.000000000000000e+000
3 5.000000000000000e001
2.500000000000000e004
4 1.000000000000000e+000
5.000000000000000e004
@@@ 122 5
The number 5 of the last line @@@ 122 5 shows the number of data points, which is missing in the above line No. Points: 0 because at the time of writing to the console it has not yet been available.
ctrl Z is not usable here in Linux, a patch to install ctrl D instead is being evaluated.
Ngspice control via input, output fifos
The following bash script (under Linux)
 launches ngspice in another thread.
 writes some commands in ngspice input
 reads the output and prints them on the console.
Example:
#!/usr/bin/env bash
NGSPICE_COMMAND="ngspice"
rm input.fifo
rm output.fifo
mkfifo input.fifo
mkfifo output.fifo
$NGSPICE_COMMAND p i <input.fifo >output.fifo &
exec 3>input.fifo
echo "I can write to input.fifo"
echo "Start processing..."
echo ""
echo "source circuit.cir" >&3
echo "unset askquit" >&3
echo "set nobreak" >&3
echo "tran 0.01ms 0.1ms">&3
echo "print n0" >&3
echo "quit" >&3
echo "Try to open output.fifo ..."
exec 4<output.fifo
echo "I can read from output.fifo"
echo "Ready to read..."
while read output
do
echo $output
done <&4
exec 3>&
exec 4>&
echo "End processing"
The input file for SPICE is:
Circuit.cir:
* Circuit.cir
V1 n0 0 SIN(0 10 1kHz)
C1 n1 n0 3.3nF
R1 0 n1 1k
.end
Compatibility
ngspice is a direct derivative of spice3f5 from UC Berkeley and thus inherits all of the commands available in its predecessor. Thanks to the open source policy of UCB (original spice3 from 1994 is still available here), several commercial variants have sprung off, either being more dedicated to IC design or more concentrating on simulating discrete and board level electronics. None of the commercial and almost none of the freely downloadable SPICE providers publishes the source code. All of them have proceeded with the development, by adding functionality, or by adding a more dedicated user interface. Some have kept the original SPICE syntax for their netlist description, others have quickly changed some if not many of the commands, functions and procedures. Thus it is difficult, if not impossible, to offer a simulator that acknowledges all of these netlist dialects. ngspice includes some features that enhance compatibility that are included automatically. This selection may be controlled to some extend by setting the compatibility mode. Others may be invoked by the user by small additions to the netlist input file. Some of them are listed in this chapter, some will be integrated into ngspice at a later stage, others will be added if they are reported by users.
Compatibility mode
The variable (17.7) ngbehavior sets the compatibility mode. 'all' is set as the default value. 'spice3' as invoked by the command
set ngbehavior=spice3
in spinit or .spiceinit will disable some of the advanced ngspice features. 'ps' will enable including a library by a simple .lib <lib_filename> statement that is not compatible to the more comfortable library handling described in Chapt. 2.7.
Missing functions
You may add one or more function definitions to your input file, as listed below.
.func LIMIT(x,a,b) {min(max(x, a), b)}
.func PWR(x,a) {abs(x) ** a}
.func PWRS(x,a) {sgn(x) * PWR(x,a)}
.func stp(x) {u(x)}
Devices
E Source with LAPLACE
see Chapt. 5.2.5.
VSwitch
The VSwitch
S1 2 3 11 0 SW
.MODEL SW VSWITCH(VON=5V VOFF=0V RON=0.1 ROFF=100K)
may become
a1 %v(11) %gd(2 3) sw
.MODEL SW aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e5
+ r_on=0.1 log=TRUE)
The XSPICE option has to be enabled.
Controls and commands
.lib
The ngspice .lib command (see 2.7) requires two parameters, a file name followed by a library name. If no library name is given, the line
.lib filename
should be replaced by
.inc filename
Alternatively, the compatibility mode (16.13.1) may be set to 'ps'.
.step
Repeated analysis in ngspice if offered by a short script inside of a .control section (see Chapt. 17.8.7) added to the input file. A simple application (multiple dc sweeps) is shown below.
Input file with parameter sweep
parameter sweep
* resistive divider, R1 swept from start_r to stop_r
* replaces .STEP R1 1k 10k 1k
R1 1 2 1k
R2 2 0 1k
VDD 1 0 DC 1
.dc VDD 0 1 .1
.control
let start_r = 1k
let stop_r = 10k
let delta_r = 1k
let r_act = start_r
* loop
while r_act le stop_r
alter r1 r_act
run
write dcsweep.out v(2)
set appendwrite
let r_act = r_act + delta_r
end
plot dc1.v(2) dc2.v(2) dc3.v(2) dc4.v(2) dc5.v(2)
+ dc6.v(2) dc7.v(2) dc8.v(2) dc9.v(2) dc10.v(2)
.endc
.end
PSPICE Compatibility mode
If the variable (17.7) ngbehavior is set to 'ps' or 'psa' with the commands
set ngbehavior=ps
or
set ngbehavior=psa
in spinit or .spiceinit, ngspice will translate all files that have been read into ngspice netlist by the .include command (ps) or the complete netlist (psa) from PSPICE syntax to ngspice. This feature allows reading of PSPICE (or TINA) compatible device libraries (ps) that are often supplied by the semiconductor device manufacturers. Or you may choose to use complete PSPICE simulation decks (psa). Some ngspice input files may fail, however. For example ngspice\examples\memristor\memristor.sp will not do, because it uses the parameter vt, and vt is a reserved word in PSPICE.
PSPICE to ngspice translation details:
 .model replacement in ako (a kind of) model descriptions
 replace the E source TABLE function by a B source pwl
 add predefined params TEMP, VT, GMIN to beginning of deck
 add predefined params TEMP, VT to beginning of each .subckt call
 add .functions limit, pwr, pwrs, stp, if, int
 replace
S1 D S DG GND SWN
.MODEL SWN VSWITCH(VON=0.55 VOFF=0.49
+ RON={1/(2*M*(W/LE)*(KPN/2)*10)} ROFF=1G)
by
as1 %vd(DG GND) % gd(D S) aswn
.model aswn aswitch(cntl_off=0.49 cntl_on=0.55
+ r_off=1G r_on={1/(2*M*(W/LE)*(KPN/2)*10)} log=TRUE)  replace & by &&
 replace  by 
 replace T_ABS by temp and T_REL_GLOBAL by dtemp
 get the area factor for diodes and bipolar devices
d1 n1 n2 dmod 7 –> d1 n1 n2 dmod area=7
q2 n1 n2 n3 [n4] bjtmod 1.35 –> q2 n1 n2 n3 n4 bjtmod area=1.35
q3 1 2 3 4 bjtmod 1.45 –> q2 1 2 3 4 bjtmod area=1.45
In ps or psa mode ngspice will treat all .lib entries like .include. There is no hierarchically library handling. So for reading HSPICE compatible libraries, you definitely have to unset the ps mode, e.g. by not adding set ngbehavior=ps or disabling it by
unset ngbehavior=ps
LTSPICE Compatibility mode
If the variable (17.7) ngbehavior is set to 'lt' or 'lta' with the commands
set ngbehavior=lt
or
set ngbehavior=lta
in spinit or .spiceinit, ngspice will translate all files that have been read into ngspice netlist by the .include command (lt) or the complete netlist (lta) from LTSPICE syntax to ngspice. This feature allows reading of LTSPICE compatible device libraries or complete netlists.
Currently we offer only a subset of the documented or undocumented functions (uplim, dnlim, uplim_tanh, dnlim_tanh). More user input is definitely required here!
This compatibility mode also adds a simple diode using the sidiode code model (chapt. 12.2.29). The diode model
d1 a k ds1
.model ds1 d(Roff=1000 Ron=0.7 Rrev=0.2 Vfwd=1
+ Vrev=10 Revepsilon=0.2 Epsilon=0.2 Ilimit=7 Revilimit=15)
is translated automatically to the equivalent code model diode
ad1 a k ads1
.model ads1 sidiode(Roff=1000 Ron=0.7 Rrev=0.2 Vfwd=1
+ Vrev=10 Revepsilon=0.2 Epsilon=0.2 Ilimit=7 Revilimit=15)
LTSPICE/PSPICE Compatibility mode
If the variable (17.7) ngbehavior is set to 'ltps' or 'ltpsa' with the commands
set ngbehavior=ltps
or
set ngbehavior=ltpsa
in spinit or .spiceinit, ngspice will translate all files that have been read into ngspice netlist by the .include command (ltps) or the complete netlist (ltpsa) 16.13.6, 16.13.5 from LTSPICE and PSPICE syntax to ngspice. This feature allows reading of LTSPICE and PSPICE compatible device libraries or complete netlists.
Tests
The ngspice distribution is accompanied by a suite of test input and output files, located in the directory ngspice/tests. Originally this suite was meant to see if ngspice with all models was made and installed properly. It is started by
$ make check
from within your compilation and development shell. A sequence of simulations is thus started, its outputs compared to given output files by comparisons string by string. This feature is momentarily used only to check for the BSIM3 model (11.2.10) and the XSPICE extension (12). Several other input files located in directory ngspice/tests may serve as lightweight examples for invoking devices and simple circuits.
Today's very complex device models (BSIM4 (see 11.2.11), HiSIM (see 11.2.15) and others) require a different strategy for verification. Under development for ngspice is the CMC Regression test by Colin McAndrew, which accompanies every new model. These tests cover a large range of different DC, AC and noise simulations with different geometry ranges and operating conditions and are more meaningful the transient simulations with their step size dependencies. A major advantage is the scalability of the diff comparisons, which check for equality within a given tolerance. A set of Perl modules cares for input, output and comparisons of the models. Currently BSIM3, BSIM4, BSIMSOI4, HiSIM, and HiSIM_HV models implement the new test. You may invoke it by running the command given above or by
$ make i check 2>&1  tee results
i will make make to ignore any errors, tee will provide console output as well as printing to file 'results'. Be aware that under MS Windows you will need the console binary (see 32.2.5) to run the CMC tests, and you have to have Perl installed!
Reporting bugs and errors
Ngspice is a complex piece of software. The source code contains over 1500 files. Various models and simulation procedures are provided, some of them not used and tested intensively. Therefore errors may be found, some still evolving from the original spice3f5 code, others introduced during the ongoing code enhancements.
If you happen to experience an error during the usage of ngspice, please send a report to the development team. Ngspice is hosted on sourceforge, the preferred place to post a bug report is the ngspice bug tracker. We would prefer to have your bug tested against the actual source code available at Git, but of course a report using the most recent ngspice release is welcome! Please provide the following information with your report:
Ngspice version
Operating system
Small input file to reproduce the bug
Actual output versus the expected output
Interactive Interpreter
Introduction
The simulation flow in ngspice (input, simulation, output) may be controlled by dot commands (see Chapt. 15 and 16.4.1) in batch mode. There is, however, a much more powerful control scheme available in ngspice, traditionally coined `Interactive Interpreter', but being much more than just that. In fact there are several ways to use this feature, truly interactively by typing commands to the input, but also running command sequences as scripts or as part of your input deck in a quasi batch mode.
You may type in expressions, functions (17.2) or commands (17.5) into the input console to elaborate on data already achieved from the interactive simulation session.
Sequences of commands, functions and control structures (17.6) may be assembled as a script (17.8) into a file, and then activated by just typing the file name into the console input of an interactive ngspice session.
Finally, and most useful, is it to add a script to the input file, in addition the the netlist and dot commands. This is achieved by enclosing the script into .control ... .endc (see 16.4.3, and 17.8.7 for an example). This feature enables a wealth of control options. You may set internal (17.7) and other variables, start a simulation, evaluate the simulation output, start a new simulation based on these data, and finally make use of many options for outputting the data (graphically or into output files).
Historical note: The final releases of Berkeley Spice introduced a command shell and scripting possibilities. The former releases were not interactive. The choice for the scripting language was an early version of `csh', the Cshell, which was en vogue back then as an improvement over the ubiquitous Bourne Shell. Berkeley Spice incorporated a modified csh source code that, instead of invoking the unix `exec' system call, executed internal SPICE C subroutines. Apart from bug fixes, this is still how ngspice works.
The cshlike scripting language is active in .control sections. It works on `strings', and does string substitution of `environment' variables. You see the csh at work in ngspice with set foo = "bar"; set baz = "bar$foo", and in if, repeat, for, ... constructs. However, ngspice processes mainly numerical data, and support for this was not available in the csh implementation. Therefore, Berkeley implemented an additional type of variables, with different syntax, to access double and complex double vectors (possibly of length 1). This new variable type is modified with let, and can be used without special syntax in places where a numerical expression is expected: let bar = 4 * 5; let zoo = bar * 4 works. Unfortunately, occasionally one has to cross the boundary between the numeric and the string domain. For this purpose the $& construct is available – it queries a variable in the numerical let domain, and expands it to a csh string denoting the value. This lets you do do something like set another = "this is $&bar". It is important to remember that set can only operate on (csh) strings, and that let operates only on numeric data. Convert from numeric to string with $&, and from string to numeric with $.
Expressions, Functions, and Constants
Ngspice and ngnutmeg store data in the form of vectors: time, voltage, etc. Each vector has a type, and vectors can be operated on and combined algebraically in ways consistent with their types. Vectors are normally created as the output of a simulation, or when a data file (output raw file) is read in again (ngspice, ngnutmeg, see the load command 17.5.40), or when the initial datafile is loaded directly into ngnutmeg. They can also be created with the let command 817.5.37).
An expression is an algebraic formula involving vectors and scalars (a scalar is a vector of length 1) and the following operations:
+  * / ^ % ,
% is the modulo operator, and the comma operator has two meanings: if it is present in the argument list of a user definable function, it serves to separate the arguments. Otherwise, the term x , y is synonymous with x + j(y). Also available are the logical operations & (and),  (or), ! (not), and the relational operations <, >, >=, <=, =, and <> (not equal). If used in an algebraic expression they work like they would in C, producing values of 0 or 1. The relational operators have the following synonyms:
Operator

Synonym

gt

>

lt

<

ge

>=

le

<=

ne

<>

and

&

or



not

!

eq

=

The operators are useful when < and > might be confused with the internal IO redirection (see 17.4, which is almost always happening). It is however safe to use < and > with the define command (17.5.15).
The following functions are available:
Name

Function

mag(vector)

Magnitude of vector (same as abs(vector)).

ph(vector)

Phase of vector.

cph(vector)

Phase of vector. Continuous values, no discontinuity at ±π.

unwrap(vector)

Phase of vector. Continuous values, no discontinuity at ±π. Real phase vector in degrees as input.

j(vector)

i(sqrt(1)) times vector.

real(vector

The real component of vector.

imag(vector)

The imaginary part of vector.

db(vector)

20 log10(mag(vector)).

log10(vector)

The logarithm (base 10) of vector.

ln(vector)

The natural logarithm (base e) of vector.

exp(vector)

e to the vector power.

abs(vector)

The absolute value of vector (same as mag).

sqrt(vector)

The square root of vector.

sin(vector)

The sine of vector.

cos(vector)

The cosine of vector.

tan(vector)

The tangent of vector.

atan(vector)

The inverse tangent of vector.

sinh(vector)

The hyperbolic sine of vector.

cosh(vector)

The hyperbolic cosine of vector.

tanh(vector)

The hyperbolic tangent of vector.

floor(vector)

Largest integer that is less than or equal to vector.

ceil(vector)

Smallest integer that is greater than or equal to vector.

norm(vector)

The vector normalized to 1 (i.e, the largest magnitude of any component is 1).

mean(vector)

The result is a scalar (a length 1 vector) that is the mean of the elements of vector (elements values added, divided by number of elements).

avg(vector)

The average of a vector. Returns a vector where each element is the mean of the preceding elements of the input vector (including the actual element). 
stddev(vector)

The result is a scalar (a length 1 vector) that is the standard deviation of the elements of vector .

group_delay(vector)

Calculates the group delay −dphase[rad]/dω[rad/s]. Input is the complex vector of a system transfer function versus frequency, resembling damping and phase per frequency value. Output is a vector of group delay values (real values of delay times) versus frequency.

vector(number)

The result is a vector of length number, with elements 0, 1, ... number  1. If number is a vector then just the first element is taken, and if it isn't an integer then the floor of the magnitude is used.

unitvec(number)

The result is a vector of length number, all elements having a value 1.

Name

Function

length(vector)

The length of vector.

interpolate(plot.vector)

The result of interpolating the named vector onto the scale of the current plot. This function uses the variable polydegree to determine the degree of interpolation.

deriv(vector)

Calculates the derivative of the given vector. This uses numeric differentiation by interpolating a polynomial and may not produce satisfactory results (particularly with iterated differentiation). The implementation only calculates the derivative with respect to the real component of that vector's scale.

vecd(vector)

Compute the differential of a vector.

vecmin(vector)

Returns the value of the vector element with minimum value. Same as minimum.

minimum(vector)

Returns the value of the vector element with minimum value. Same as vecmin.

vecmax(vector)

Returns the value of the vector element with maximum value. Same as maximum.

maximum(vector)

Returns the value of the vector element with maximum value. Same as vecmax.

fft(vector)

fast fourier transform (17.5.27)

ifft(vector)

inverse fast fourier transform (17.5.27)

sortorder(vector)

Returns a vector with the positions of the elements in a real vector after they have been sorted into increasing order using a stable method (qsort).

timer(vector)

Returns CPUtime minus the value of the first vector element.

clock(vector)

Returns walltime minus the value of the first vector element.

Several functions offering statistical procedures are listed in the following table:
Name

Function

rnd(vector)

A vector with each component a random integer between 0 and the absolute value of the input vector's corresponding integer element value.

sgauss(vector)

Returns a vector of random numbers drawn from a Gaussian distribution (real value, mean = 0 , standard deviation = 1). The length of the vector returned is determined by the input vector. The contents of the input vector will not be used. A call to sgauss(0) will return a single value of a random number as a vector of length 1..

sunif(vector)

Returns a vector of random real numbers uniformly distributed in the interval [1 .. 1[. The length of the vector returned is determined by the input vector. The contents of the input vector will not be used. A call to sunif(0) will return a single value of a random number as a vector of length 1.

poisson(vector)

Returns a vector with its elements being integers drawn from a Poisson distribution. The elements of the input vector (real numbers) are the expected numbers λ. Complex vectors are allowed, real and imaginary values are treated separately.

exponential(vector)

Returns a vector with its elements (real numbers) drawn from an exponential distribution. The elements of the input vector are the respective mean values (real numbers). Complex vectors are allowed, real and imaginary values are treated separately.

An input vector may be either the name of a vector already defined or a floatingpoint number (a scalar). A scalar will result in an output vector of length 1. A number may be written in any format acceptable to ngspice, such as 14.6Meg or 1.231e4. Note that you can either use scientific notation or one of the abbreviations like MEG or G, but not both. As with ngspice, a number may have trailing alphabetic characters.
The notation expr [num] denotes the num'th element of expr. For multidimensional vectors, a vector of one less dimension is returned. Also for multidimensional vectors, the notation expr[m][n] will return the nth element of the mth subvector. To get a subrange of a vector, use the form expr[lower, upper]. To reference vectors in a plot that is not the current plot (see the setplot command, below), the notation plotname.vecname can be used. Either a plotname or a vector name may be the wildcard all. If the plotname is all, matching vectors from all plots are specified, and if the vector name is all, all vectors in the specified plots are referenced. Note that you may not use binary operations on expressions involving wildcards  it is not obvious what all + all should denote, for instance. Thus some (contrived) examples of expressions are:
Expressions examples:
cos(TIME) + db(v(3))
sin(cos(log([1 2 3 4 5 6 7 8 9 10])))
TIME * rnd(v(9))  15 * cos(vin#branch) ^ [7.9e5 8]
not ((ac3.FREQ[32] & tran1.TIME[10]) gt 3)
(sunif(0) ge 0) ? 1.0 : 2.0
mag(fft(v(18)))
Vector names in ngspice may look like @dname[param], where dname is either the name of a device instance or of a device model. The vector contains the value of the parameter of the device or model. See Appendix, Chapt. 31 for details of which parameters are available. The returned value is a vector of length 1. Please note that finding the value of device and device model parameters can also be done with the show command (e.g. show v1 : dc).
There are a number of predefined constants in ngspice, which you may use by their name. They are stored in plot (17.3) const and are listed in the table below:
Name

Description

Value

pi

π

3.14159...

e

e (the base of natural logarithms)

2.71828...

c

c (the speed of light)

299,792,500 $\frac{m}{sec}$

i

i (the square root of 1)

$\sqrt{ 1}$

kelvin

(absolute zero in centigrade)

273.15C

echarge

q (the charge of an electron)

1.60219e19 C

boltz

k (Boltzmann's constant)

1.38062e23$\frac{J}{K}$

planck

h (Planck's constant)

6.62620e34

yes

boolean

1

no

boolean

0

TRUE

boolean

1

FALSE

boolean

0

These constants are all given in MKS units. If you define another variable with a name that conflicts with one of these then it takes precedence.
Additional constants may be generated during circuit setup (see .csparam, 2.10).
Plots
The output vectors of any analysis are stored in plots, a traditional SPICE notion. A plot is a group of vectors. A first tran command will generate several vectors within a plot tran1. A subsequent tran command will store their vectors in tran2. Then a linearize command will linearize all vectors from tran2 and store them in tran3, which then becomes the current plot. A fft will generate a plot spec1, again now the current plot. The display command always will show all vectors in the current plot. Echo $plots followed by Return lists all plots generated so far**. **Setplot followed by Return will show all plots and ask for a (new) plot to become current. A simple Return will end the command. Setplot name will change the current plot to 'name' (e.g. setplot tran2 will make tran2 the current plot). A sequence name.vector may be used to access the vector from a foreign plot.
You may generate plots by yourself: setplot new will generate a new plot named unknown1, set curplottitle=”a new plot” will set a title, set curplotname=myplot will set its name as a short description, set curplotdate=”Sat Aug 28 10:49:42 2010” will set its date. Note that strings with spaces have to be given with double quotes.
Of course the notion 'plot' will be used by this manual also in its more common meaning, denoting a graphics plot or being a plot command. Be careful to get the correct meaning.
Command Interpretation
On the console
On the ngspice console window (or into the Windows GUI) you may directly type in any command from 17.5. Within a command sequence Input/output redirection is available (see Chapt. 17.8.8 for an example)  the symbols >, >>, >&, >>&, and < have the same effects as in the Cshell. This I/Oredirection is internal to ngspice commands, and should not be mixed up with the `external' I/Oredirection offered by the usual shells (Linux, MSYS etc.), see 17.5.69. You may type multiple commands on one line, separated by semicolons.
Scripts
If a word is typed as a command, and there is no builtin command with that name, the directories in the sourcepath list are searched in order for a file with the name given by the word. If it is found, it is read in as a command file (as if it were sourced). Before it is read, however, the variables argc and argv are set to the number of words following the filename on the command line, and a list of those words respectively. After the file is finished, these variables are unset. Note that if a command file calls another, it must save its argv and argc since they are altered. Also, command files may not be reentrant since there are no local variables. Of course, the procedures may explicitly manipulate a stack.... This way one can write scripts analogous to shell scripts for ngnutmeg and ngspice.
Note that for the script to work with ngspice, it must begin with a blank line (or whatever else, since it is thrown away) and then a line with .control on it. This is an unfortunate result of the source command being used for both circuit input and command file execution. Note also that this allows the user to merely type the name of a circuit file as a command and it is automatically run. The commands are executed immediately, without running any analyses that may be specified in the circuit (to execute the analyses before the script executes, include a run command in the script).
There are various command scripts installed in /usr/local/lib/spice/scripts (or whatever the path is on your machine), and the default sourcepath includes this directory, so you can use these command files (almost) like builtin commands.
Addon to circuit file
The probably most common way to invoke the commands described in the following Chapt. 17.5 is to add a .control ... .endc section to the circuit input file (see 16.4.3).
Example:
.control
pre_set strict_errorhandling
unset ngdebug
*save outputs and specials
save x1.x1.x1.7 V(9) V(10) V(11) V(12) V(13)
run
display
* plot the inputs, use offset to plot on top of each other
plot v(1) v(2)+4 v(3)+8 v(4)+12 v(5)+16 v(6)+20 v(7)+24 v(8)+28
* plot the outputs, use offset to plot on top of each other
plot v(9) v(10)+4 v(11)+8 v(12)+12 v(13)+16
.endc
Commands
Commands marked with a * are only available in ngspice, not in ngnutmeg.
Ac*: Perform an AC, smallsignal frequency response analysis
General Form:
ac ( DEC  OCT  LIN ) N Fstart Fstop
Do an small signal ac analysis (see also Chapt. 15.3.1) over the specified frequency range.
DEC decade variation, and N is the number of points per decade.
OCT stands for octave variation, and N is the number of points per octave.
LIN stands for linear variation, and N is the number of points.
fstart is the starting frequency, and fstop is the final frequency.
Note that in order for this analysis to be meaningful, at least one independent source must have been specified with an ac value.
In this ac analysis all nonlinear devices are linearized around their actual dc operating point. All Ls and Cs get their imaginary value, depending on the actual frequency step. Each output vector will be calculated relative to the input voltage (current) given by the ac value (Iin equals to 1 in the example below). The resulting node voltages (and branch currents) are complex vectors. Therefore you have to be careful using the plot command.
Example:
* AC test
Iin 1 0 AC 1
R1 1 2 100
L1 2 0 1
.control
AC LIN 101 10 10K
plot v(2) $ real part !
plot mag(v(2)) $ magnitude
plot db(v(2)) $ same as vdb(2)
plot imag(v(2)) $ imaginary part of v(2)
plot real(v(2)) $ same as plot v(2)
plot phase(v(2)) $ phase in rad
plot cph(v(2)) $ phase in rad, continuous beyond pi
plot 180/PI*phase(v(2)) $ phase in deg
.endc
.end
In addition to the plot examples given above you may use the variants of vxx(node) described in Chapt. 15.6.2 like vdb(2). An option to suppress OP analysis before AC may be set for linear circuits (15.1.3).
Alias: Create an alias for a command
General Form:
alias [word] [text ...]
Causes word to be aliased to text. History substitutions may be used, as in Cshell aliases.
Alter*: Change a device or model parameter
Alter changes the value for a device or a specified parameter of a device or model.
General Form:
alter dev = <expression>
alter dev param = <expression>
alter @dev[param] = <expression>
<expression> must be real (complex isn't handled right now, integer is fine though, but no strings. For booleans, use 0/1).
Old style (pre 3f4):
alter device value
alter device parameter value [ parameter value ]
Using the old style, its first form is used by simple devices that have one principal value (resistors, capacitors, etc.) where the second form is for more complex devices (bjt's, etc.). Model parameters can be changed with the second form if the name contains a `#'. For specifying a list of parameters as values, start it with `[', followed by the values in the list, and end with `]'. Be sure to place a space between each of the values and before and after the `[' and `]'.
Some examples are given below:
Examples (Spice3f4 style):
alter vd = 0.1
alter vg dc = 0.6
alter @m1[w]= 15e06
alter @vg[sin] [ 1 1.5 2MEG ]
alter @Vi[pwl] = [ 0 1.2 100p 0 ]
alter may have vectors (17.8.2) or variables (17.8.1) as parameters.
Examples (vector or variable in parameter list):
let newfreq = 10k
alter @vg[sin] [ 1 1.5 $&newfreq ] $ vector
set newperiod = 150u
alter @Vi[pwl] = [ 0 1.2 $newperiod 0 ] $ variable
You may change a parameter of a device residing in a subcircuit, e.g. of MOS transistor msub1 in subcircuit xm1 (see also Chapt. 31.1).
Examples (parameter of device in subcircuit):
alter m.xm1.msub1 w = 20u
alter @m.xm1.msub1[w] = 20u
Altermod*: Change model parameter(s)
General form:
altermod mod param = <expression>
altermod @mod[param] = <expression>
Example:
altermod nc1 tox = 10e9
altermod @nc1[tox] = 10e9
Altermod operates on models and is used to change model parameters. The above example will change the parameter tox in all devices using the model nc1, which is defined as
*** BSIM3v3 model
.MODEL nc1 nmos LEVEL=8 version = 3.2.2
+ acm = 2 mobmod = 1 capmod = 1 noimod = 1
+ rs = 2.84E+03 rd = 2.84E+03 rsh = 45
+ tox = 20E9 xj = 0.25E6 nch = 1.7E+17
+ ...
If you invoke the model by the MOS device
M1 d g s b nc1 w=10u l=1u
you might also insert the device name M1 for mod as in
altermod M1 tox = 10e9
The model parameter tox will be modified, however not only for device M1, but for all devices using the associated MOS model nc1!
If you want to run corner simulations within a single simulation flow, the following option of altermod may be of help. The parameter set with name modn may be overrun by the altermod command specifying a model file. All parameter values fitting to the existing model modn will be modified. As usual the 'reset' command (see 17.5.55) restores the original values. The model file (see 2.3) has to use the standard specifications for an input file, the .model section is the relevant part. However the first line in the model file will be ignored by the input parser, so it should contain only some title information. The .model statement should appear then in the second or any later line. More than one .model section may reside in the file.
General form:
altermod mod1 [mod2 .. mod15] file = <model file name>
altermod mod1 [mod2 .. mod15] file <model file name>
Example:
altermod nch file = BSIM3_nmos.mod
altermod pch nch file BSIM4_mos.mod
Be careful that the new model file corresponds to the existing model selected by modn. The existing models are defined during circuit setup at start up of ngspice. Models have been included by .model statements (2.3) in your input file or included by the .include command. In the example given above, the models nch (or nch and pch) have to be already available before calling altermod. If they are not found in the active circuit, ngspice will terminate with an error message. There is no checking however of the version and level parameters! So you have to be responsible for offering model data of the same model level (e.g. level 8 for BSIM3). Thus no new model is selectable by altermod, but the parameters of the existing model(s) may be changed (partially, completely, temporarily).
Alterparam*: Change value of a global parameter
General form:
alterparam paramname=pvalue
alterparam subname paramname=pvalue
Example (global, top level parameter):
.param npar = 5
...
alterparam npar = 7 $ change npar from 5 to 7
reset
Example (parameter in a subcircuit):
.subckt sname
.param subpar = 13
...
.ends
...
alterparam sname subpar = 11 $ change subpar from 13 to 11
reset
Alterparam operates on global parameters or on parameters in a subcircuit defined by the .param ... statement. A subsequent call to reset (17.5.55) is required for the parameter value change to become effective.
Asciiplot: Plot values using oldstyle character plots
General Form:
asciiplot plotargs
Produce a line printer plot of the vectors. The plot is sent to the standard output, or you can put it into a file with asciiplot args ... > file. The set options width, height, and nobreak determine the width and height of the plot, and whether there are page breaks, respectively. The 'more' mode is the standard mode if printing to the screen, that is after a number of lines given by height, and after a page break printing stops with request for answering the prompt by <return>, 'c' or 'q'. If everything shall be printed without stopping, put the command set nomoremode into .spiceinit 16.6 (or spinit 16.5). Note that you will have problems if you try to asciiplot something with an Xscale that isn't monotonic (i.e, something like sin(TIME) ), because asciiplot uses a simpleminded linear interpolation. The asciiplot command doesn't deal with log scales or the delta keywords.
Aspice*: Asynchronous ngspice run
General Form:
aspice inputfile [outputfile]
Start an ngspice run, and when it is finished load the resulting data. The raw data is kept in a temporary file. If outputfile is specified then the diagnostic output is directed into that file, otherwise it is thrown away.
Bug: Mail a bug report
General Form:
bug
Send a bug report. Please include a short summary of the problem, the version number and name of the operating system that you are running, the version of ngspice that you are running, and the relevant ngspice input file. (If you have defined BUGADDR, the mail is delivered to there.)
Cd: Change directory
General Form:
cd [directory]
Change the current working directory to directory, or to the user's home directory (Linux: HOME, MS Windows: USERPROFILE), if none is given.
Cdump: Dump the control flow to the screen
General Form:
cdump
Dumps the control sequence to the screen (all statements inside the .control ... .endc structure before the line with cdump). Indentations show the structure of the sequence. The example below is printed if you add cdump to /examples/Monte_Carlo/MonteCarlo.sp.
Example (abbreviated):
let mc_runs=5
let run=0
...
define agauss(nom, avar, sig) (nom + avar/sig * sgauss(0))
define limit(nom, avar) (nom + ((sgauss(0) >=0) ? avar : avar))
dowhile run < mc_runs
alter c1=unif(1e09, 0.1)
...
ac oct 100 250k 10meg
meas ac bw trig vdb(out) val=10 rise=1 targ vdb(out)
+ val=10 fall=1
set run="$&run"
...
let run=run + 1
end
plot db({$scratch}.allv)
echo
print {$scratch}.bwh
cdump
Circbyline*: Enter a circuit line by line
General Form:
circbyline line
Enter a circuit line by line. line is any circuit line, as found in the *.cir ngspice input files. The first line is a title line. The entry will be finished by entering .end. Circuit parsing is then started automatically.
Example:
circbyline test circuit
circbyline v1 1 0 1
circbyline r1 1 0 1
circbyline .dc v1 0.5 1.5 0.1
circbyline .end
run
plot i(v1)
Codemodel*: Load an XSPICE code model library
General Form:
codemodel [library file]
Load a XSPICE code model shared library file (e.g. analog.cm ...). Only available if ngspice is compiled with the XSPICE option (enablexspice) or with the Windows executable distributed since ngspice21. This command has to be called from spinit (see Chapt. 16.5) (or .spiceinit for personal code models, 16.6).
Compose: Compose a vector
General Form:
compose name values value1 [ value2 ... ]
compose name param = val [ param = val ... ]
The first form takes the values and creates a new vector, where the values may be arbitrary expressions.
The second form has the following possible parameters:
start

The value of name[0]

stop

The last value of name

step

The difference between successive elements of the created vector

lin

How many linearly spaced elements the new vector should have

log

The number of points, logarithmically spaced (not working)

dec

The number of points per decade, logarithmically spaced (not working)

center

Where to center the range of points (not working)

span

The size of the range of points (not working)

gauss

The nominal value for the used Gaussian distribution

sd

The standard deviation for the used Gaussian distribution

sigma

The sigma for the used Gaussian distribution

random

The nominal value for a uniform random distribution

rvar

The percentage variation for the uniform random distribution

Dc*: Perform a DCsweep analysis
General Form:
dc Source Vstart Vstop Vincr [ Source2 Vstart2 Vstop2 Vincr2 ]
Do a dc transfer curve analysis. See the previous Chapt. 15.3.2 for more details. Several options may be set (15.1.2).
Define: Define a function
General Form:
define function(arg1, arg2, ...) expression
Define the function with the name function and arguments arg1, arg2, ... to be expression, which may involve the arguments. When the function is later used, the arguments it is given are substituted for the formal arguments when it was parsed. If expression is not present, any existing definition for function is printed, and if there are no arguments then all expressions for all currently active definitions are printed. Note that you may have different functions defined with the same name but different arities. Some useful definitions are:
Example:
define max(x,y) (x > y) * x + (x <= y) * y
define min(x,y) (x < y) * x + (x >= y) * y
define limit(nom, avar) (nom + ((sgauss(0) >= 0) ? avar : avar))
Deftype: Define a new type for a vector or plot
General Form:
deftype [v  p] typename abbrev
defines types for vectors and plots. abbrev will be used to parse things like abbrev(name) and to label axes with M<abbrev>, instead of numbers. It may be omitted. Also, the command `deftype p plottype pattern ...' will assign plottype as the name to any plot with one of the patterns in its Name: field.
Example:
deftype v capacitance F
settype capacitance moscap
plot moscap vs v(cc)
Delete*: Remove a trace or breakpoint
General Form:
delete [ debugnumber ... ]
Delete the specified saved nodes and parameters, breakpoints and traces. The debug numbers are those shown by the status command (unless you do status > file, in which case the debug numbers are not printed).
Destroy: Delete an output data set
General Form:
destroy [plotnames  all]
Release the memory holding the output data (the given plot or all plots) for the specified runs.
Devhelp: information on available devices
General Form:
devhelp [[csv] device_name [parameter]]
Devhelp command shows the user information about the devices available in the simulato