NAME_TABLE:

C_Function_Name: cm_d_srlatch

Spice_Model_Name: d_srlatch

Description: "digital sr-type latch"

PORT_TABLE:

Port Name: s r

Description: "set" "reset"

Direction: in in

Default_Type: d d

Allowed_Types: [d] [d]

Vector: no no

Vector_Bounds: - -

Null_Allowed: no no

PORT_TABLE:

Port Name: enable

Description: "enable"

Direction: in

Default_Type: d

Allowed_Types: [d]

Vector: no

Vector_Bounds: -

Null_Allowed: no

PORT_TABLE:

Port Name: set reset

Description: "set" "reset"

Direction: in in

Default_Type: d d

Allowed_Types: [d] [d]

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PORT_TABLE:

Port Name: out Nout

Description: "data output" "inverted data output"

Direction: out out

Default_Type: d d

Allowed_Types: [d] [d]

Vector: no no

Vector_Bounds: - -

Null_Allowed: no no

PARAMETER_TABLE:

Parameter_Name: sr_delay

Description: "delay from s or r input change"

Data_Type: real

Default_Value: 1.0e-9

Limits: [1.0e-12 -]

Vector: no

Vector_Bounds: -

Null_Allowed: yes

PARAMETER_TABLE:

Parameter_Name: enable_delay set_delay

Description: "delay from enable" "delay from SET"

Data_Type: real real

Default_Value: 1.0e-9 1.0e-9

Limits: [1.0e-12 -] [1.0e-12 -]

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PARAMETER_TABLE:

Parameter_Name: reset_delay ic

Description: "delay from RESET" "output initial state"

Data_Type: real boolean

Default_Value: 1.0e-9 0

Limits: [1.0e-12 -] -

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PARAMETER_TABLE:

Parameter_Name: sr_load enable_load

Description: "s & r input loads (F)" "enable load value (F)"

Data_Type: real real

Default_Value: 1.0e-12 1.0e-12

Limits: - -

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PARAMETER_TABLE:

Parameter_Name: set_load reset_load

Description: "set load value (F)" "reset load (F)"

Data_Type: real real

Default_Value: 1.0e-12 1.0e-12

Limits: - -

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PARAMETER_TABLE:

Parameter_Name: rise_delay fall_delay

Description: "rise delay" "fall delay"

Data_Type: real real

Default_Value: 1.0e-9 1.0e-9

Limits: [1.0e-12 -] [1.0e-12 -]

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

• Description:
  The digital sr-type latch is a one-bit, level-sensitive storage element that will output the value dictated by the state of the s and r pins whenever the enable input line is high (ONE). This value is stored (i.e., held on the out line) whenever the enable line is low (ZERO). The particular value chosen is as shown below:

s=ZERO, r=ZERO => out=current value (i.e., not change in output)

s=ZERO, r=ONE => out=ZERO

s=ONE, r=ZERO => out=ONE

s=ONE, r=ONE => out=UNKNOWN

Asynchronous set and reset signals exist, and each of the four methods of changing the stored output of the d srlatch (i.e., s/r combination changing with enable=ONE, enable changing to ONE from ZERO with an output-changing combination of s and r, raising set and raising reset) have separate delays associated with them. You may also specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies.

Note that any UNKNOWN inputs other than on the s and r lines when enable=ZERO immediately cause the output to go UNKNOWN.

Example SPICE Usage:

a4 12 4 5 6 3 14 16 latch2

.model latch2 d_srlatch(sr_delay = 13.0e-9 enable_delay = 22.0e-9

+ set_delay = 25.0e-9

+ reset_delay = 27.0e-9 ic = 2

+ rise_delay = 10.0e-9 fall_delay = 3e-9)