NAME_TABLE:

C_Function_Name: cm_d_srff

Spice_Model_Name: d_srff

Description: "digital set-reset flip flop"

PORT_TABLE:

Port Name: s r

Description: "set input" "reset input"

Direction: in in

Default_Type: d d

Allowed_Types: [d] [d]

Vector: no no

Vector_Bounds: - -

Null_Allowed: no no

PORT_TABLE:

Port Name: clk

Description: "clock"

Direction: in

Default_Type: d

Allowed_Types: [d]

Vector: no

Vector_Bounds: -

Null_Allowed: no

PORT_TABLE:

Port Name: set reset

Description: "asynchronous set" "asynchronous reset"

Direction: in in

Default_Type: d d

Allowed_Types: [d] [d]

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PORT_TABLE:

Port Name: out Nout

Description: "data output" "inverted data output"

Direction: out out

Default_Type: d d

Allowed_Types: [d] [d]

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PARAMETER_TABLE:

Parameter_Name: clk_delay set_delay

Description: "delay from clk" "delay from set"

Data_Type: real real

Default_Value: 1.0e-9 1.0e-9

Limits: [1.0e-12 -] [1.0e-12 -]

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PARAMETER_TABLE:

Parameter_Name: reset_delay ic

Description: "delay from reset" "output initial state"

Data_Type: real int

Default_Value: 1.0e-9 0

Limits: [1.0e-12 -] [0 2]

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PARAMETER_TABLE:

Parameter_Name: sr_load clk_load

Description: "set/reset loads (F)" "clk load value (F)"

Data_Type: real real

Default_Value: 1.0e-12 1.0e-12

Limits: - -

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PARAMETER_TABLE:

Parameter_Name: set_load reset_load

Description: "set load value (F)" "reset load (F)"

Data_Type: real real

Default_Value: 1.0e-12 1.0e-12

Limits: - -

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PARAMETER_TABLE:

Parameter_Name: rise_delay fall_delay

Description: "rise delay" "fall delay"

Data_Type: real real

Default_Value: 1.0e-9 1.0e-9

Limits: [1.0e-12 -] [1.0e-12 -]

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

• Description:
  The digital sr-type flip flop is a one-bit, edge-triggered storage element that will store data whenever the clk input line transitions from low to high (ZERO to ONE). The value stored (i.e., the out value) will depend on the s and r input pin values, and will be:

out=ONE if s=ONE and r=ZERO;

out=ZERO if s=ZERO and r=ONE;

out=previous value if s=ZERO and r=ZERO;

out=UNKNOWN if s=ONE and r=ONE;

In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_srff have separate load values and delays associated with them. You may also specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies.

Note that any UNKNOWN inputs other than s and r immediately cause the output to go UNKNOWN.

Example SPICE Usage:

a8 2 12 4 5 6 3 14 flop7

.model flop7 d_srff(clk_delay = 13.0e-9 set_delay = 25.0e-9

+ reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9

+ fall_delay = 3e-9)