NAME_TABLE:

C_Function_Name: cm_d_dff

Spice_Model_Name: d_dff

Description: "digital d-type flip flop"

PORT_TABLE:

Port Name: data clk

Description: "input data" "clock"

Direction: in in

Default_Type: d d

Allowed_Types: [d] [d]

Vector: no no

Vector_Bounds: - -

Null_Allowed: no no

PORT_TABLE:

Port Name: set reset

Description: "asynch. set" "asynch. reset"

Direction: in in

Default_Type: d d

Allowed_Types: [d] [d]

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PORT_TABLE:

Port Name: out Nout

Description: "data output" "inverted data output"

Direction: out out

Default_Type: d d

Allowed_Types: [d] [d]

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PARAMETER_TABLE:

Parameter_Name: clk_delay set_delay

Description: "delay from clk" "delay from set"

Data_Type: real real

Default_Value: 1.0e-9 1.0e-9

Limits: [1.0e-12 -] [1.0e-12 -]

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PARAMETER_TABLE:

Parameter_Name: reset_delay ic

Description: "delay from reset" "output initial state"

Data_Type: real int

Default_Value: 1.0e-9 0

Limits: [1.0e-12 -] [0 2]

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PARAMETER_TABLE:

Parameter_Name: data_load clk_load

Description: "data load value (F)" "clk load value (F)"

Data_Type: real real

Default_Value: 1.0e-12 1.0e-12

Limits: - -

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PARAMETER_TABLE:

Parameter_Name: set_load reset_load

Description: "set load value (F)" "reset load (F)"

Data_Type: real real

Default_Value: 1.0e-12 1.0e-12

Limits: - -

Vector: no no

Vector.Bounds: - -

Null_Allowed: yes yes

PARAMETER_TABLE:

Parameter_Name: rise_delay fall_delay

Description: "rise delay" "fall delay"

Data_Type: real real

Default_Value: 1.0e-9 1.0e-9

Limits: [1.0e-12 -] [1.0e-12 -]

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

• Description:
  The digital d-type flip flop is a one-bit, edge-triggered storage element that will store data whenever the clk input line transitions from low to high (ZERO to ONE). In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_dff have separate load values and delays associated with them. Additionally, you may specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies.
  Note that any UNKNOWN input on the set or reset lines immediately results in an UNKNOWN output.

Example SPICE Usage:

a7 1 2 3 4 5 6 flop1

.model flop1 d_dff(clk_delay = 13.0e-9 set_delay = 25.0e-9

+ reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9

+ fall_delay = 3e-9)