NAME_TABLE:

C_Function_Name: cm_d_and

Spice_Model_Name: d_and

Description: "digital `and' gate"

PORT_TABLE:

Port Name: in out

Description: "input" "output"

Direction: in out

Default_Type: d d

Allowed_Types: [d] [d]

Vector: yes no

Vector_Bounds: [2 -] -

Null_Allowed: no no

PARAMETER_TABLE:

Parameter_Name: rise_delay fall_delay

Description: "rise delay" "fall delay"

Data_Type: real real

Default_Value: 1.0e-9 1.0e-9

Limits: [1.0e-12 -] [1.0e-12 -]

Vector: no no

Vector_Bounds: - -

Null_Allowed: yes yes

PARAMETER_TABLE:

Parameter_Name: input_load

Description: "input load value (F)"

Data_Type: real

Default_Value: 1.0e-12

Limits: -

Vector: no

Vector_Bounds: -

Null_Allowed: yes

• Description:
  The digital and gate is an n-input, single-output and gate that produces an active `1' value if, and only if, all of its inputs are also `1' values. If ANY of the inputs is a `0', the output will also be a `0'; if neither of these conditions holds, the output will be unknown. The delays associated with an output rise and those associated with an output fall may be specified independently. The model also posts an input load value (in farads) based on the parameter input load. The output of this model does not, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays.

Example SPICE Usage:

a6 [1 2] 8 and1

.model and1 d_and(rise_delay = 0.5e-9 fall_delay = 0.3e-9

+ input_load = 0.5e-12)