NAME_TABLE:

C_Function_Name: cm_multi_input_pwl

Spice_Model_Name: multi_input_pwl

Description: "multi_input_pwl block"

PORT_TABLE:

Port_Name: in out

Description: "input array" "output"

Direction: in out

Default_Type: vd vd

Allowed_Types: [vd,id] [vd,id]

Vector: yes no

Vector_Bounds: [2 -] -

Null_Allowed: no no

PARAMETER_TABLE:

Parameter_Name: x y

Description: "x array" "y array"

Data_Type: real real

Default_Value: 0.0 0.0

Limits: - -

Vector: yes yes

Vector_Bounds: [2 -] [2 -]

Null_Allowed: no no

PARAMETER_TABLE:

Parameter_Name: model

Description: "model type"

Data_Type: string

Default_Value: "and"

Limits: -

Vector: no

Vector_Bounds: -

Null_Allowed: yes

• Description:
  Multi-input gate voltage controlled voltage source that supports and or or gating. The x's and y's represent the piecewise linear variation of output (y) as a function of input (x). The type of gate is selectable by the parameter model. In case the model is and, the smallest input determines the output value (i.e. the and function). In case the model is or, the largest input determines the output value (i.e. the or function). The inverse of these functions (i.e. nand and nor) is constructed by complementing the y array.

Example SPICE Usage:

a82 [1 0 2 0 3 0] 7 0 pwlm

.

.

.model pwlm multi_input_pwl((x=[-2.0 -1.0 2.0 4.0 5.0]

+ y=[-0.2 -0.2 0.1 2.0 10.0]

+ model="and")