JFET level 2 Parker Skellern model
The level 2 model is an improvement to level 1. Details are available from Macquarie University. Some important items are:
- The description maintains strict continuity in its high-order derivatives, which is essential for prediction of distortion and intermodulation.
- Frequency dependence of output conductance and transconductance is described as a function of bias.
- Both drain-gate and source-gate potentials modulate the pinch-off potential, which is consistent with S-parameter and pulsed-bias measurements.
- Self-heating varies with frequency.
- Extreme operating regions - subthreshold, forward gate bias, controlled resistance, and breakdown regions - are included.
- Parameters provide independent fitting to all operating regions. It is not necessary to compromise one region in favor of another.
- Strict drain-source symmetry is maintained. The transition during drain-source potential reversal is smooth and continuous.
The model equations are described in this pdf document and in [19].
Name
|
Description
|
Units
|
Default
|
ID
|
Device IDText
|
Text
|
PF1
|
ACGAM
|
Capacitance modulation
|
-
|
0
|
BETA
|
Linear-region transconductance scale
|
-
|
10−4
|
CGD
|
Zero-bias gate-source capacitance
|
F
|
0
|
CGS
|
Zero-bias gate-drain capacitance
|
F
|
0
|
DELTA
|
Thermal reduction coefficient
|
$\frac{1}{W}$
|
0
|
FC
|
Forward bias capacitance parameter
|
-
|
0.5
|
HFETA
|
High-frequency VGS feedback parameter
|
-
|
0
|
HFE1
|
HFGAM modulation by VGD
|
$\frac{1}{V}$
|
0
|
HFE2
|
HFGAM modulation by VGS
|
$\frac{1}{V}$
|
0
|
HFGAM
|
High-frequency VGD feedback parameter
|
-
|
0
|
HFG1
|
HFGAM modulation by VSG
|
$\frac{1}{V}$
|
0
|
HFG2
|
HFGAM modulation by VDG
|
$\frac{1}{V}$
|
0
|
IBD
|
Gate-junction breakdown current
|
A
|
0
|
IS
|
Gate-junction saturation current
|
A
|
10−14
|
LFGAM
|
Low-frequency feedback parameter
|
-
|
0
|
LFG1
|
LFGAM modulation by VSG
|
$\frac{1}{V}$
|
0
|
LFG2
|
LFGAM modulation by VDG
|
$\frac{1}{V}$
|
0
|
MVST
|
Subthreshold modulation
|
$\frac{1}{V}$
|
0
|
N
|
Gate-junction ideality factor
|
-
|
1
|
P
|
Linear-region power-law exponent
|
-
|
2
|
Q
|
Saturated-region power-law exponent
|
-
|
2
|
RS
|
Source ohmic resistance
|
Ω
|
0
|
RD
|
Drain ohmic resistance
|
Ω
|
0
|
TAUD
|
Relaxation time for thermal reduction
|
s
|
0
|
TAUG
|
Relaxation time for gamma feedback
|
s
|
0
|
VBD
|
Gate-junction breakdown potential
|
V
|
1
|
VBI
|
Gate-junction potential
|
V
|
1
|
VST
|
Subthreshold potential
|
V
|
0
|
VTO
|
Threshold voltage
|
V
|
-2.0
|
XC
|
Capacitance pinch-off reduction factor
|
-
|
0
|
XI
|
Saturation-knee potential factor
|
-
|
1000
|
Z
|
Knee transition parameter
|
-
|
0.5
|
RG
|
Gate ohmic resistance
|
Ω
|
0
|
LG
|
Gate inductance
|
H
|
0
|
LS
|
Source inductance
|
H
|
0
|
LD
|
Drain inductance
|
H
|
0
|
CDSS
|
Fixed Drain-source capacitance
|
F
|
0
|
AFAC
|
Gate-width scale factor
|
-
|
1
|
NFING
|
Number of gate fingers scale factor
|
-
|
1
|
TNOM
|
Nominal Temperature (Not implemented)
|
K
|
300 K
|
TEMP
|
Temperature
|
K
|
300 K
|