Preface
Introduction
1.
Simulation Algorithms
1.1.
Analog Simulation
1.2.
Digital Simulation
1.3.
Mixed-Signal Simulation
1.4.
User-Defined Nodes
1.5.
Mixed-Level Simulation
1.6.
CIDER (DSIM)
1.7.
GSS TCAD
2.
Supported Analyses
2.1.
DC Analysis
2.2.
AC Small-Signal Analysis
2.3.
Transient Analysis
2.4.
Pole-Zero Analysis
2.5.
Small-Signal Distortion Analysis
2.6.
Sensitivity Analysis
2.7.
Noise Analysis
2.8.
Periodic Steady State Analysis
3.
Analysis at Different Temperatures
4.
Convergence
4.1.
Voltage convergence criterion
4.2.
Current convergence criterion
4.3.
Convergence failure
5.
Circuit Description
5.1.
General Structure and Conventions
5.1.1.
Input file structure
5.1.2.
Circuit elements (device instances)
5.1.3.
Some naming conventions
5.2.
Basic lines
5.2.1.
.TITLE line
5.2.2.
.END Line
5.2.3.
Comments
5.2.4.
End-of-line comments
5.3.
.MODEL Device Models
5.4.
.SUBCKT Subcircuits
5.4.1.
.SUBCKT Line
5.4.2.
.ENDS Line
5.4.3.
Subcircuit Calls
5.5.
.GLOBAL
5.6.
.INCLUDE
5.7.
.LIB
5.8.
.PARAM Parametric netlists
5.8.1.
.param line
5.8.2.
Brace expressions in circuit elements:
5.8.3.
Subcircuit parameters
5.8.4.
Symbol scope
5.8.5.
Syntax of expressions
5.8.6.
Reserved words
5.8.7.
A word of caution on the three ngspice expression parsers
5.9.
.FUNC
5.10.
.CSPARAM
5.11.
.TEMP
5.12.
.IF Condition-Controlled Netlist
5.13.
Parameters, functions, expressions, and command scripts
5.13.1.
Parameters
5.13.2.
Nonlinear sources
5.13.3.
Control commands, Command scripts
6.
Circuit Elements and Models
6.1.
General options and information
6.1.1.
Paralleling devices with multiplier m
6.1.2.
Instance and model parameters
6.1.3.
Model binning
6.1.4.
Initial conditions
6.2.
Elementary Devices
6.2.1.
Resistors
6.2.2.
Semiconductor Resistors
6.2.3.
Semiconductor Resistor Model (R)
6.2.4.
Resistors, dependent on expressions (behavioral resistor)
6.2.5.
Capacitors
6.2.6.
Semiconductor Capacitors
6.2.7.
Semiconductor Capacitor Model (C)
6.2.8.
Capacitors, dependent on expressions (behavioral capacitor)
6.2.9.
Inductors
6.2.10.
Inductor model
6.2.11.
Coupled (Mutual) Inductors
6.2.12.
Inductors, dependent on expressions (behavioral inductor)
6.2.13.
Capacitor or inductor with initial conditions
6.2.14.
Switches
6.2.15.
Switch Model (SW/CSW)
7.
Voltage and Current Sources
7.1.
Independent Sources for Voltage or Current
7.1.1.
Pulse
7.1.2.
Sinusoidal
7.1.3.
Exponential
7.1.4.
Piece-Wise Linear
7.1.5.
Single-Frequency FM
7.1.6.
Amplitude modulated source (AM)
7.1.7.
Transient noise source
7.1.8.
Random voltage source
7.1.9.
External voltage or current input
7.1.10.
Arbitrary Phase Sources
7.2.
Linear Dependent Sources
7.2.1.
Gxxxx: Linear Voltage-Controlled Current Sources (VCCS)
7.2.2.
Exxxx: Linear Voltage-Controlled Voltage Sources (VCVS)
7.2.3.
Fxxxx: Linear Current-Controlled Current Sources (CCCS)
7.2.4.
Hxxxx: Linear Current-Controlled Voltage Sources (CCVS)
7.2.5.
Polynomial Source Compatibility
8.
Non-linear Dependent Sources (Behavioral Sources)
8.1.
Bxxxx: Nonlinear dependent source (ASRC)
8.1.1.
Syntax and usage
8.1.2.
Special B-Source Variables time, temper, hertz
8.1.3.
par('expression')
8.1.4.
Piecewise Linear Function: pwl
8.2.
Exxxx: non-linear voltage source
8.2.1.
VOL
8.2.2.
VALUE
8.2.3.
TABLE
8.2.4.
POLY
8.2.5.
LAPLACE
8.3.
Gxxxx: non-linear current source
8.3.1.
CUR
8.3.2.
VALUE
8.3.3.
TABLE
8.3.4.
POLY
8.3.5.
LAPLACE
8.3.6.
Example
8.4.
Debugging a behavioral source
8.5.
POLY Sources
8.5.1.
E voltage source, G current source
8.5.2.
F voltage source, H current source
9.
Transmission Lines
9.1.
Lossless Transmission Lines
9.2.
Lossy Transmission Lines
9.2.1.
Lossy Transmission Line Model (LTRA)
9.3.
Uniform Distributed RC Lines
9.3.1.
Uniform Distributed RC Model (URC)
9.4.
KSPICE Lossy Transmission Lines
9.4.1.
Single Lossy Transmission Line (TXL)
9.4.2.
Coupled Multiconductor Line (CPL)
10.
Diodes
10.1.
Junction Diodes
10.2.
Diode Model (D)
10.2.1.
Junction DC parameters
10.2.2.
Junction capacitance parameters
10.2.3.
Temperature effects
10.2.4.
Noise modeling
10.3.
Diode Equations
10.3.1.
Parameters Scaling
10.3.2.
Diode DC, Transient and AC model equations
10.3.3.
Temperature dependence
10.3.4.
Noise model
11.
BJTs
11.1.
Bipolar Junction Transistors (BJTs)
11.2.
BJT Models (NPN/PNP)
11.2.1.
Gummel-Poon BJT Parameters (incl. model extensions)
12.
JFETs
12.1.
Junction Field-Effect Transistors (JFETs)
12.2.
JFET Models (NJF/PJF)
12.2.1.
JFET level 1 model with Parker Skellern modification
12.2.2.
JFET level 2 Parker Skellern model
13.
MESFETs
13.1.
MESFETs
13.2.
MESFET Models (NMF/PMF)
13.2.1.
Model by Statz e.a.
13.2.2.
Model by Ytterdal e.a.
13.2.3.
hfet1
13.2.4.
hfet2
14.
MOSFETs
14.1.
MOSFET devices
14.2.
MOSFET models (NMOS/PMOS)
14.2.1.
MOS Level 1
14.2.2.
MOS Level 2
14.2.3.
MOS Level 3
14.2.4.
MOS Level 6
14.2.5.
Notes on Level 1-6 models
14.2.6.
NGSPICE level 1, 2, 3 and 6 parameters
14.2.7.
MOS Level 9
14.2.8.
BSIM Models
14.2.9.
BSIM1 model (level 4)
14.2.10.
Ngspice BSIM (level 4) parameters
14.2.11.
BSIM2 model (level 5)
14.2.12.
BSIM3 model (levels 8, 49)
14.2.13.
BSIM4 model (levels 14, 54)
14.2.14.
EKV model
14.2.15.
BSIMSOI models (levels 10, 58, 55, 56, 57)
14.2.16.
SOI3 model (level 60)
14.2.17.
HiSIM models of the University of Hiroshima
14.3.
Power MOSFET model (VDMOS)
14.3.1.
NGSPICE VDMOS parameters
15.
Mixed-Mode and Behavioral Modeling with XSPICE
15.1.
Code Model Element & .MODEL Cards
15.1.1.
Syntax
15.1.2.
Examples
15.1.3.
Search path for file input
15.2.
Analog Models
15.2.1.
Gain
15.2.2.
Summer
15.2.3.
Multiplier
15.2.4.
Divider
15.2.5.
Limiter
15.2.6.
Controlled Limiter
15.2.7.
PWL Controlled Source
15.2.8.
Filesource
15.2.9.
multi_input_pwl block
15.2.10.
Analog Switch
15.2.11.
Zener Diode
15.2.12.
Current Limiter
15.2.13.
Hysteresis Block
15.2.14.
Differentiator
15.2.15.
Integrator
15.2.16.
S-Domain Transfer Function
15.2.17.
Slew Rate Block
15.2.18.
Inductive Coupling
15.2.19.
Magnetic Core
15.2.20.
Controlled Sine Wave Oscillator
15.2.21.
Controlled Triangle Wave Oscillator
15.2.22.
Controlled Square Wave Oscillator
15.2.23.
Controlled One-Shot
15.2.24.
Capacitance Meter
15.2.25.
Inductance Meter
15.2.26.
Memristor
15.2.27.
2D table model
15.2.28.
3D table model
15.2.29.
Simple Diode Model
15.3.
Hybrid Models
15.3.1.
Digital-to-Analog Node Bridge
15.3.2.
Analog-to-Digital Node Bridge
15.3.3.
Controlled Digital Oscillator
15.3.4.
Node bridge from digital to real with enable
15.3.5.
A Z**-1 block working on real data
15.3.6.
A gain block for event-driven real data
15.3.7.
Node bridge from real to analog voltage
15.4.
Digital Models
15.4.1.
Buffer
15.4.2.
Inverter
15.4.3.
And
15.4.4.
Nand
15.4.5.
Or
15.4.6.
Nor
15.4.7.
Xor
15.4.8.
Xnor
15.4.9.
Tristate
15.4.10.
Pullup
15.4.11.
Pulldown
15.4.12.
D Flip Flop
15.4.13.
JK Flip Flop
15.4.14.
Toggle Flip Flop
15.4.15.
Set-Reset Flip Flop
15.4.16.
D Latch
15.4.17.
Set-Reset Latch
15.4.18.
State Machine
15.4.19.
Frequency Divider
15.4.20.
RAM
15.4.21.
Digital Source
15.4.22.
LUT
15.4.23.
General LUT
15.5.
Predefined Node Types for event driven simulation
15.5.1.
Digital Node Type
15.5.2.
Real Node Type
15.5.3.
Int Node Type
15.5.4.
(Digital) Input/Output
16.
Verilog A Device models
16.1.
Introduction
16.2.
ADMS
16.3.
How to integrate a Verilog-A model into ngspice
16.3.1.
How to setup a *.va model for ngspice
16.3.2.
Adding admsXml to your build environment
16.3.3.
Compile ngspice with ADMS
17.
Mixed-Level Simulation (ngspice with TCAD)
17.1.
Cider
17.2.
GSS, Genius
18.
Analyses and Output Control (batch mode)
18.1.
Simulator Variables (.options)
18.1.1.
General Options
18.1.2.
DC Solution Options
18.1.3.
Matrix Conditioning info
18.1.4.
AC Solution Options
18.1.5.
Transient Analysis Options
18.1.6.
ELEMENT Specific options
18.1.7.
Transmission Lines Specific Options
18.1.8.
Precedence of option and .options commands
18.2.
Initial Conditions
18.2.1.
.NODESET: Specify Initial Node Voltage Guesses
18.2.2.
.IC: Set Initial Conditions
18.3.
Analyses
18.3.1.
.AC: Small-Signal AC Analysis
18.3.2.
.DC: DC Transfer Function
18.3.3.
.DISTO: Distortion Analysis
18.3.4.
.NOISE: Noise Analysis
18.3.5.
.OP: Operating Point Analysis
18.3.6.
.PZ: Pole-Zero Analysis
18.3.7.
.SENS: DC or Small-Signal AC Sensitivity Analysis
18.3.8.
.TF: Transfer Function Analysis
18.3.9.
.TRAN: Transient Analysis
18.3.10.
Transient noise analysis (at low frequency)
18.3.11.
.PSS: Periodic Steady State Analysis
18.4.
Measurements after AC, DC and Transient Analysis
18.4.1.
.meas(ure)
18.4.2.
batch versus interactive mode
18.4.3.
General remarks
18.4.4.
Input
18.4.5.
Trig Targ
18.4.6.
Find ... When
18.4.7.
AVG|MIN|MAX|PP|RMS|MIN_AT|MAX_AT
18.4.8.
Integ
18.4.9.
param
18.4.10.
par('expression')
18.4.11.
Deriv
18.4.12.
More examples
18.5.
Safe Operating Area (SOA) warning messages
18.5.1.
Resistor and Capacitor SOA model parameters
18.5.2.
Diode SOA model parameter
18.5.3.
BJT SOA model parameter
18.5.4.
MOS SOA model parameter
18.6.
Batch Output
18.6.1.
.SAVE: Name vector(s) to be saved in raw file
18.6.2.
.PRINT Lines
18.6.3.
.PLOT Lines
18.6.4.
.FOUR: Fourier Analysis of Transient Analysis Output
18.6.5.
.PROBE: Name vector(s) to be saved in raw file
18.6.6.
par('expression'): Algebraic expressions for output
18.6.7.
.width
18.7.
Measuring current through device terminals
18.7.1.
Adding a voltage source in series
18.7.2.
Using option 'savecurrents'
19.
Starting ngspice
19.1.
Introduction
19.2.
Where to obtain ngspice
19.3.
Command line options for starting ngspice and ngnutmeg
19.4.
Starting options
19.4.1.
Batch mode
19.4.2.
Interactive mode
19.4.3.
Control mode (Interactive mode with control file or control section)
19.5.
Standard configuration file spinit
19.6.
User defined configuration file .spiceinit
19.7.
Environmental variables
19.7.1.
Ngspice specific variables
19.7.2.
Common environment variables
19.8.
Memory usage
19.9.
Simulation time
19.10.
Ngspice on multi-core processors using OpenMP
19.10.1.
Introduction
19.10.2.
Internals
19.10.3.
Some results
19.10.4.
Usage
19.10.5.
Literature
19.11.
Server mode option -s
19.12.
Ngspice control via input, output fifos
19.13.
Compatibility
19.13.1.
Compatibility mode
19.13.2.
Missing functions
19.13.3.
Devices
19.13.4.
E Source with LAPLACE
19.13.5.
VSwitch
19.13.6.
Controls and commands
19.13.7.
.lib
19.13.8.
.step
19.13.9.
PSPICE Compatibility mode
19.13.10.
LTSPICE Compatibility mode
19.13.11.
LTSPICE/PSPICE Compatibility mode
19.14.
Tests
19.15.
Reporting bugs and errors
20.
Interactive Interpreter
20.1.
Introduction
20.2.
Expressions, Functions, and Constants
20.3.
Plots
20.4.
Command Interpretation
20.4.1.
On the console
20.4.2.
Scripts
20.4.3.
Add-on to circuit file
20.5.
Commands
20.5.1.
Ac*: Perform an AC, small-signal frequency response analysis
20.5.2.
Alias: Create an alias for a command
20.5.3.
Alter*: Change a device or model parameter
20.5.4.
Altermod*: Change model parameter(s)
20.5.5.
Alterparam*: Change value of a global parameter
20.5.6.
Asciiplot: Plot values using old-style character plots
20.5.7.
Aspice*: Asynchronous ngspice run
20.5.8.
Bug: Mail a bug report
20.5.9.
Cd: Change directory
20.5.10.
Cdump: Dump the control flow to the screen
20.5.11.
Circbyline*: Enter a circuit line by line
20.5.12.
Codemodel*: Load an XSPICE code model library
20.5.13.
Compose: Compose a vector
20.5.14.
Dc*: Perform a DC-sweep analysis
20.5.15.
Define: Define a function
20.5.16.
Deftype: Define a new type for a vector or plot
20.5.17.
Delete*: Remove a trace or breakpoint
20.5.18.
Destroy: Delete an output data set
20.5.19.
Devhelp: information on available devices
20.5.20.
Diff: Compare vectors
20.5.21.
Display: List known vectors and types
20.5.22.
Echo: Print text
20.5.23.
Edit*: Edit the current circuit
20.5.24.
Edisplay: Print a list of all the event nodes
20.5.25.
Eprint: Print an event driven node
20.5.26.
Eprvcd: Dump event nodes in VCD format
20.5.27.
FFT: fast Fourier transform of vectors
20.5.28.
specwindow:
20.5.29.
specwindoworder:
20.5.30.
Fourier: Perform a Fourier transform
20.5.31.
Getcwd: Print the current working directory
20.5.32.
Gnuplot: Graphics output via gnuplot
20.5.33.
Hardcopy: Save a plot to a file for printing
20.5.34.
Help: Print summaries of Ngspice commands
20.5.35.
History: Review previous commands
20.5.36.
Inventory: Print circuit inventory
20.5.37.
Iplot*: Incremental plot
20.5.38.
Jobs*: List active asynchronous ngspice runs
20.5.39.
Let: Assign a value to a vector
20.5.40.
Linearize*: Interpolate to a linear scale
20.5.41.
Listing*: Print a listing of the current circuit
20.5.42.
Load: Load rawfile data
20.5.43.
Mc_source*: Reload the circuit netlist from an internal storage
20.5.44.
Meas*: Measurements on simulation data
20.5.45.
Mdump*: Dump the matrix values to a file (or to console)
20.5.46.
Mrdump*: Dump the matrix right hand side values to a file (or to console)
20.5.47.
Noise*: Noise analysis
20.5.48.
Op*: Perform an operating point analysis
20.5.49.
Option*: Set a ngspice option
20.5.50.
Plot: Plot vectors on the display
20.5.51.
Pre_
: execute commands prior to parsing the circuit
20.5.52.
Print: Print values
20.5.53.
Psd: power spectral density of vectors
20.5.54.
Quit: Leave Ngspice or Nutmeg
20.5.55.
Rehash: Reset internal hash tables
20.5.56.
Remcirc*: Remove the current circuit
20.5.57.
Reset*: Reset an analysis
20.5.58.
Reshape: Alter the dimensionality or dimensions of a vector
20.5.59.
Resume*: Continue a simulation after a stop
20.5.60.
Rspice*: Remote ngspice submission
20.5.61.
Run*: Run analysis from the input file
20.5.62.
Rusage: Resource usage
20.5.63.
Save*: Save a set of outputs
20.5.64.
Sens*: Run a sensitivity analysis
20.5.65.
Set: Set the value of a variable
20.5.66.
Setcirc*: Change the current circuit
20.5.67.
Setplot: Switch the current set of vectors
20.5.68.
Setscale: Set the scale vector for the current plot
20.5.69.
Setseed: Set the seed value for the random number generator
20.5.70.
Settype: Set the type of a vector
20.5.71.
Shell: Call the command interpreter
20.5.72.
Shift: Alter a list variable
20.5.73.
Show*: List device state
20.5.74.
Showmod*: List model parameter values
20.5.75.
Snload*: Load the snapshot file
20.5.76.
Snsave*: Save a snapshot file
20.5.77.
Source: Read a ngspice input file
20.5.78.
Spec: Create a frequency domain plot
20.5.79.
Status*: Display breakpoint information
20.5.80.
Step*: Run a fixed number of time-points
20.5.81.
Stop*: Set a breakpoint
20.5.82.
Strcmp: Compare two strings
20.5.83.
Sysinfo*: Print system information
20.5.84.
Tf*: Run a Transfer Function analysis
20.5.85.
Trace*: Trace nodes
20.5.86.
Tran*: Perform a transient analysis
20.5.87.
Transpose: Swap the elements in a multi-dimensional data set
20.5.88.
Unalias: Retract an alias
20.5.89.
Undefine: Retract a definition
20.5.90.
Unlet: Delete the specified vector(s)
20.5.91.
Unset: Clear a variable
20.5.92.
Version: Print the version of ngspice
20.5.93.
Where*: Identify troublesome node or device
20.5.94.
Wrdata: Write data to a file (simple table)
20.5.95.
Write: Write data to a file (Spice3f5 format)
20.5.96.
Wrs2p: Write scattering parameters to file (Touchstone® format)
20.6.
Control Structures
20.6.1.
While - End
20.6.2.
Repeat - End
20.6.3.
Dowhile - End
20.6.4.
Foreach - End
20.6.5.
If - Then - Else
20.6.6.
Label
20.6.7.
Goto
20.6.8.
Continue
20.6.9.
Break
20.7.
Internally predefined variables
20.8.
Scripts
20.8.1.
Variables
20.8.2.
Vectors
20.8.3.
Commands
20.8.4.
control structures
20.8.5.
Example script 'spectrum'
20.8.6.
Example script for random numbers
20.8.7.
Parameter sweep
20.8.8.
Output redirection
20.9.
Scattering parameters (s-parameters)
20.9.1.
Intro
20.9.2.
S-parameter measurement basics
20.9.3.
Usage
20.10.
MISCELLANEOUS
20.11.
Bugs
21.
Ngspice User Interfaces
21.1.
MS Windows Graphical User Interface
21.2.
MS Windows Console
21.3.
Linux
21.4.
CygWin
21.5.
Error handling
21.6.
Postscript printing options
21.7.
Gnuplot
21.8.
Integration with CAD software and `third party' GUIs
21.8.1.
KiCad
21.8.2.
GNU Spice GUI
21.8.3.
XCircuit
21.8.4.
GEDA
21.8.5.
MSEspice
21.8.6.
GNU Octave
22.
ngspice as shared library or dynamic link library
22.1.
Compile options
22.1.1.
How to get the sources
22.1.2.
Linux, MINGW, CYGWIN
22.1.3.
MS Visual Studio
22.2.
Linking shared ngspice to a calling application
22.2.1.
Linking during creating the caller
22.2.2.
Loading at runtime
22.3.
Shared ngspice API
22.3.1.
structs and types defined for transporting data
22.3.2.
Exported functions
22.3.3.
int ngSpice_Init(SendChar*, SendStat*, ControlledExit*, SendData*, SendInitData*, BGThreadRunning*, void)
22.3.4.
Pointers to callback functions (details see 19.3.3):
22.3.5.
int ngSpice_Init_Sync(GetVSRCData* , GetISRCData* , GetSyncData* , int*, void*)
22.3.6.
int ngSpice_Command(char*)
22.3.7.
bool ngSpice_running (void)
22.3.8.
pvector_info ngGet_Vec_Info(char*)
22.3.9.
int ngSpice_Circ(char**)
22.3.10.
char* ngSpice_CurPlot(void)
22.3.11.
char** ngSpice_AllPlots(void)
22.3.12.
char** ngSpice_AllVecs(char*)
22.3.13.
bool ngSpice_SetBkpt(double)
22.3.14.
int ngSpice_Init_Evt(SendEvtData*, SendInitEvtData*, void*)
22.3.15.
Pointers to callback functions (details see 19.3.3):
22.3.16.
pevt_shared_data ngGet_Evt_NodeInfo(char*)
22.3.17.
char** ngSpice_AllEvtNodes(void)
22.3.18.
Callback functions
22.3.19.
typedef int (SendChar)(char*, int, void*)
22.3.20.
typedef int (SendStat)(char*, int, void*)
22.3.21.
typedef int (ControlledExit)(int, bool, bool, int, void*)
22.3.22.
typedef int (SendData)(pvecvaluesall, int, int, void*)
22.3.23.
typedef int (SendInitData)(pvecinfoall, int, void*)
22.3.24.
typedef int (BGThreadRunning)(bool, int, void*)
22.3.25.
Callback functions addresses received from caller with ngSpice_Init_Evt() function:
22.3.26.
typedef int (SendEvtData)(int, double, double, char *, void , int, int, int, void)
22.3.27.
typedef int (SendInitEvtData)(int, int, char*, char*, int, void*)
22.4.
General remarks on using the API
22.4.1.
Loading a netlist
22.4.2.
Loading from file
22.4.3.
Loading line by line
22.4.4.
Loading as a string array
22.4.5.
Using a .control section
22.4.6.
Running the simulation
22.4.7.
Accessing data
22.4.8.
Synchronous access
22.4.9.
Asynchronous access
22.4.10.
XSPICE event node data
22.4.11.
Altering model or device parameters
22.4.12.
Output
22.4.13.
Error handling
22.5.
Example applications
22.6.
ngspice parallel
22.6.1.
Go parallel!
22.6.2.
Additional exported functions
22.6.3.
int ngSpice_Init_Sync(GetVSRCData* , GetISRCData* , GetSyncData* , int*, void*)
22.6.4.
Pointers to callback functions (details see 19.3.3):
22.6.5.
More pointers
22.6.6.
bool ngSpice_SetBkpt(double)
22.6.7.
Additional callback functions
22.6.8.
typedef int (GetVSRCData)(double*, double, char*, int, void*)
22.6.9.
typedef int (GetISRCData)(double*, double, char*, int, void*)
22.6.10.
typedef int (GetSyncData)(double, double*, double, int, void*)
22.6.11.
Parallel ngspice example
23.
TCLspice
23.1.
tclspice framework
23.2.
tclspice documentation
23.3.
spicetoblt
23.4.
Running TCLspice
23.5.
examples
23.5.1.
Active capacitor measurement
23.5.2.
Invocation:
23.5.3.
testbench1.tcl
23.5.4.
Optimization of a linearization circuit for a Thermistor
23.5.5.
Invocation:
23.5.6.
testbench3.tcl
23.5.7.
NOTE:
23.5.8.
As component values are modified by a spice::alter
23.5.9.
Component values can be considered as global variable.
23.5.10.
R10 and R12 are not passed to iteration function
23.5.11.
because it is expected to be correct, i.e. to
23.5.12.
have been modified soon before
23.5.13.
NOTE:
23.5.14.
As the library is executed once for the
23.5.15.
whole script execution, it is important to manage the memory
23.5.16.
and regularly destroy unused data set. The data
23.5.17.
computed here will not be reused. Clean it
23.5.18.
Progressive display
23.5.19.
testbench2.tcl
23.6.
Compiling
23.6.1.
Linux
23.6.2.
MS Windows
23.6.3.
Downloads
23.6.4.
Tcl
23.6.5.
Tk
23.6.6.
blt
23.6.7.
tclspice
23.7.
MS Windows 32 Bit binaries
24.
Example Circuits
24.1.
AC coupled transistor amplifier
24.2.
Differential Pair
24.3.
MOSFET Characterization
24.4.
RTL Inverter
24.5.
Four-Bit Binary Adder (Bipolar)
24.6.
Four-Bit Binary Adder (MOS)
24.7.
Transmission-Line Inverter
25.
Statistical circuit analysis
25.1.
Introduction
25.2.
Using random param(eters)
25.3.
Behavioral sources (B, E, G, R, L, C) with random control
25.4.
ngspice scripting language
25.5.
Monte-Carlo Simulation
25.5.1.
Example 1
25.5.2.
Example 2
25.5.3.
Example 3
25.6.
Data evaluation with Gnuplot
26.
Circuit optimization with ngspice
26.1.
Optimization of a circuit
26.2.
ngspice optimizer using ngspice scripts
26.3.
ngspice optimizer using tclspice
26.4.
ngspice optimizer using a Python script
26.5.
ngspice optimizer using ASCO
26.5.1.
Three stage operational amplifier
26.5.2.
amp3.cfg
26.5.3.
amp3.sp
26.5.4.
n.typ, p.typ
26.5.5.
Testing the set-up
26.5.6.
Running the simulation
26.5.7.
Digital inverter
26.5.8.
Bandpass
26.5.9.
Class-E power amplifier
27.
Notes
27.1.
Glossary
27.2.
Acronyms and Abbreviations
27.3.
To Do
27.4.
Bibliography
28.
XSPICE Basics
28.1.
ngspice with the XSPICE option
28.2.
The XSPICE Code Model Subsystem
28.3.
XSPICE Top-Level Diagram
29.
Execution Procedures
29.1.
Simulation and Modeling Overview
29.1.1.
Describing the Circuit
29.1.2.
Example Circuit Description Input
29.1.3.
Models and Subcircuits
29.1.4.
Device Models
29.1.5.
Subcircuits
29.1.6.
XSPICE Code Models
29.1.7.
Node Bridge Models
29.1.8.
Practical Model Development
29.2.
Circuit Description Syntax
29.2.1.
XSPICE Syntax Extensions
29.2.2.
Convergence Debugging Support
29.2.3.
Digital Nodes
29.2.4.
User-Defined Nodes
29.2.5.
Supply Ramping
29.3.
How to create code models
30.
Example circuits
Light
(default)
Rust
Coal
Navy
Ayu
Transmission Lines Specific Options
TRYTOCOMPACT
Applicable only to the LTRA model (see
6.2.1
). When specified, the simulator tries to condense an LTRA transmission line's past history of input voltages and currents.